Tag Archives: Gedeng Ruan

Better RRAM memory devices in the short term

Given my recent spate of posts about computing and the future of the chip (list to follow at the end of this post), this Rice University [Texas, US] research suggests that some improvements to current memory devices might be coming to the market in the near future. From a July 12, 2014 news item on Azonano,

Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

A July 10, 2014 Rice University news release, which originated the news item, provides more detail,

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Here’s a link to and a citation for the paper,

Nanoporous Silicon Oxide Memory by Gunuk Wang, Yang Yang, Jae-Hwang Lee, Vera Abramova, Huilong Fei, Gedeng Ruan, Edwin L. Thomas, and James M. Tour. Nano Lett., Article ASAP DOI: 10.1021/nl501803s Publication Date (Web): July 3, 2014

Copyright © 2014 American Chemical Society

This paper is behind a paywall.

As for my recent spate of posts on computers and chips, there’s a July 11, 2014 posting about IBM, a 7nm chip, and much more; a July 9, 2014 posting about Intel and its 14nm low-power chip processing and plans for a 10nm chip; and, finally, a June 26, 2014 posting about HP Labs and its plans for memristive-based computing and their project dubbed ‘The Machine’.

James’ bond (Rice University research team creates graphene/nanotube hybrid)

I have to give credit to Mike Williams’ Nov. 27, 2012 Rice University news release for the “James’ bond” phrase used to describe this graphene/nanotube hybrid,

A seamless graphene/nanotube hybrid created at Rice University may be the best electrode interface material possible for many energy storage and electronics applications.

Led by Rice chemist James Tour, researchers have successfully grown forests of carbon nanotubes that rise quickly from sheets of graphene to astounding lengths of up to 120 microns, according to a paper published today by Nature Communications. A house on an average plot with the same aspect ratio would rise into space.

Seven-atom rings (in red) at the transition from graphene to nanotube make this new hybrid material a seamless conductor. The hybrid may be the best electrode interface material possible for many energy storage and electronics applications. Image courtesy of the Tour Group

The Rice hybrid combines two-dimensional graphene, which is a sheet of carbon one atom thick, and nanotubes into a seamless three-dimensional structure. The bonds between them are covalent, which means adjacent carbon atoms share electrons in a highly stable configuration. The nanotubes aren’t merely sitting on the graphene sheet; they become a part of it.

“Many people have tried to attach nanotubes to a metal electrode and it’s never gone very well because they get a little electronic barrier right at the interface,” Tour said. “By growing graphene on metal (in this case copper) and then growing nanotubes from the graphene, the electrical contact between the nanotubes and the metal electrode is ohmic. That means electrons see no difference, because it’s all one seamless material.

In the new work, the team grew a specialized odako that retained the iron catalyst and aluminum oxide buffer but put them on top of a layer of graphene grown separately on a copper substrate. The copper stayed to serve as an excellent current collector for the three-dimensional hybrids that were grown within minutes to controllable lengths of up to 120 microns.

Electron microscope images showed the one-, two- and three-walled nanotubes firmly embedded in the graphene, and electrical testing showed no resistance to the flow of current at the junction.

“The performance we see in this study is as good as the best carbon-based supercapacitors that have ever been made,” Tour said. “We’re not really a supercapacitor lab, and still we were able to match the performance because of the quality of the electrode. It’s really remarkable, and it all harkens back to that unique interface.”

Here’s the citation and a link for the article,

A seamless three-dimensional carbon nanotube graphene hybrid material by Yu Zhu, Lei Li, Chenguang Zhang, Gilberto Casillas,  Zhengzong Sun, Zheng Yan, Gedeng Ruan, Zhiwei Peng, Abdul-Rahman O. Raji, Carter Kittrell, Robert H. Hauge & James M. Tour in Nature Communications 3, Article number:1225 doi:10.1038/ncomms2234 Published 27 November 2012

This article is behind a paywall.

Graphene dreams of the Morph

For anyone who’s not familiar with the Morph, it’s an idea that Nokia and the University of Cambridge’s Nanoscience Centre have been working on for the last few years. Originally announced as a type of flexible phone that you could wrap around your wrist, the Morph is now called a concept.  Here’s an animation illustrating some of the concepts which include flexibility and self-cleaning,

There have been very few announcements of any kind about the Morph or the technology that will support this concept. A few months ago, they did make an announcement about researching graphene as a means of actualizing the concept (noted in my May 6, 2011 posting [scroll down about 1/2 way]).

Interestingly the latest research published  on graphene and the flexible, transparent screens that are necessary to making something like the Morph a reality has come from a lab at Rice University. From the August 1, 2011 news item on Nanowerk,

The lab of Rice chemist James Tour lab has created thin films that could revolutionize touch-screen displays, solar panels and LED lighting. The research was reported in the online edition of ACS Nano (“Rational Design of Hybrid Graphene Films for High-Performance Transparent Electrodes”).

Flexible, see-through video screens may be the “killer app” that finally puts graphene — the highly touted single-atom-thick form of carbon — into the commercial spotlight once and for all, Tour said. Combined with other flexible, transparent electronic components being developed at Rice and elsewhere, the breakthrough could lead to computers that wrap around the wrist and solar cells that wrap around just about anything. [emphasis mine]

The lab’s hybrid graphene film is a strong candidate to replace indium tin oxide (ITO), a commercial product widely used as a transparent, conductive coating. It’s the essential element in virtually all flat-panel displays, including touch screens on smart phones and iPads, and is part of organic light-emitting diodes (OLEDs) and solar cells.

Here’s James Tour and Yu Zhu, the paper’s lead author, explaining how the flexible screen was developed,

There are other flexible screens and competitors to the Morph notably the PaperPhone mentioned in my May 6,2011 posting (scroll down about 2/3 of the way) and in my May 12, 2011 posting featuring an interview with Roel Vertegaal of Queen’s University, Ontario, Canada, about the PaperPhone. (We did not discuss the role that graphene might or might not play in the development of the Paperphone’s screens.)

I wonder what impact this work at Rice will have not only for the Morph and the PaperPhone but on the European Union’s pathfinder research competition (the prize is $1B Euros), mentioned in my June 13, 2011 posting about graphene (scroll down about 1/3 of the way). Graphene is one of the research areas being considered for the prize.

ETA Aug. 5, 2011: Tour’s team just published another paper on graphene, one that proves you can make it from anything containing carbon according the Aug. 4, 2011 news item, One Box of Girl Scout Cookies Worth $15 Billion: Lab Shows Troop How Any Carbon Source Can Become Valuable Graphene, on Science Daily,

The cookie gambit started on a dare when Tour mentioned at a meeting that his lab had produced graphene from table sugar.

“I said we could grow it from any carbon source — for example, a Girl Scout cookie, because Girl Scout Cookies were being served at the time,” Tour recalled. “So one of the people in the room said, ‘Yes, please do it. … Let’s see that happen.'”

Members of Girl Scouts of America Troop 25080 came to Rice’s Smalley Institute for Nanoscale Science and Technology to see the process. Rice graduate students Gedeng Ruan, lead author of the paper, and Zhengzong Sun calculated that at the then-commercial rate for pristine graphene — $250 for a two-inch square — a box of traditional Girl Scout shortbread cookies could turn a $15 billion profit.

Here’s the full reference for this second paper,

Gedeng Ruan, Zhengzong Sun, Zhiwei Peng, James M. Tour. Growth of Graphene from Food, Insects and Waste. ACS Nano, 2011; 110729113834087 DOI: 10.1021/nn202625c

The article is behind a paywall.