Tag Archives: Michael Arnold

Carbon nanotubes that can outperform silicon

According to a Sept. 2, 2016 news item on phys.org, researchers at the University of Wisconsin-Madison have produced carbon nanotube transistors that outperform state-of-the-art silicon transistors,

For decades, scientists have tried to harness the unique properties of carbon nanotubes to create high-performance electronics that are faster or consume less power—resulting in longer battery life, faster wireless communication and faster processing speeds for devices like smartphones and laptops.

But a number of challenges have impeded the development of high-performance transistors made of carbon nanotubes, tiny cylinders made of carbon just one atom thick. Consequently, their performance has lagged far behind semiconductors such as silicon and gallium arsenide used in computer chips and personal electronics.

Now, for the first time, University of Wisconsin-Madison materials engineers have created carbon nanotube transistors that outperform state-of-the-art silicon transistors.

Led by Michael Arnold and Padma Gopalan, UW-Madison professors of materials science and engineering, the team’s carbon nanotube transistors achieved current that’s 1.9 times higher than silicon transistors. …

A Sept. 2, 2016 University of Wisconsin-Madison news release (also on EurekAlert) by Adam Malecek, which originated the news item, describes the research in more detail and notes that the technology has been patented,

“This achievement has been a dream of nanotechnology for the last 20 years,” says Arnold. “Making carbon nanotube transistors that are better than silicon transistors is a big milestone. This breakthrough in carbon nanotube transistor performance is a critical advance toward exploiting carbon nanotubes in logic, high-speed communications, and other semiconductor electronics technologies.”

This advance could pave the way for carbon nanotube transistors to replace silicon transistors and continue delivering the performance gains the computer industry relies on and that consumers demand. The new transistors are particularly promising for wireless communications technologies that require a lot of current flowing across a relatively small area.

As some of the best electrical conductors ever discovered, carbon nanotubes have long been recognized as a promising material for next-generation transistors.

Carbon nanotube transistors should be able to perform five times faster or use five times less energy than silicon transistors, according to extrapolations from single nanotube measurements. The nanotube’s ultra-small dimension makes it possible to rapidly change a current signal traveling across it, which could lead to substantial gains in the bandwidth of wireless communications devices.

But researchers have struggled to isolate purely carbon nanotubes, which are crucial, because metallic nanotube impurities act like copper wires and disrupt their semiconducting properties — like a short in an electronic device.

The UW–Madison team used polymers to selectively sort out the semiconducting nanotubes, achieving a solution of ultra-high-purity semiconducting carbon nanotubes.

“We’ve identified specific conditions in which you can get rid of nearly all metallic nanotubes, where we have less than 0.01 percent metallic nanotubes,” says Arnold.

Placement and alignment of the nanotubes is also difficult to control.

To make a good transistor, the nanotubes need to be aligned in just the right order, with just the right spacing, when assembled on a wafer. In 2014, the UW–Madison researchers overcame that challenge when they announced a technique, called “floating evaporative self-assembly,” that gives them this control.

The nanotubes must make good electrical contacts with the metal electrodes of the transistor. Because the polymer the UW–Madison researchers use to isolate the semiconducting nanotubes also acts like an insulating layer between the nanotubes and the electrodes, the team “baked” the nanotube arrays in a vacuum oven to remove the insulating layer. The result: excellent electrical contacts to the nanotubes.

The researchers also developed a treatment that removes residues from the nanotubes after they’re processed in solution.

“In our research, we’ve shown that we can simultaneously overcome all of these challenges of working with nanotubes, and that has allowed us to create these groundbreaking carbon nanotube transistors that surpass silicon and gallium arsenide transistors,” says Arnold.

The researchers benchmarked their carbon nanotube transistor against a silicon transistor of the same size, geometry and leakage current in order to make an apples-to-apples comparison.

They are continuing to work on adapting their device to match the geometry used in silicon transistors, which get smaller with each new generation. Work is also underway to develop high-performance radio frequency amplifiers that may be able to boost a cellphone signal. While the researchers have already scaled their alignment and deposition process to 1 inch by 1 inch wafers, they’re working on scaling the process up for commercial production.

Arnold says it’s exciting to finally reach the point where researchers can exploit the nanotubes to attain performance gains in actual technologies.

“There has been a lot of hype about carbon nanotubes that hasn’t been realized, and that has kind of soured many people’s outlook,” says Arnold. “But we think the hype is deserved. It has just taken decades of work for the materials science to catch up and allow us to effectively harness these materials.”

The researchers have patented their technology through the Wisconsin Alumni Research Foundation.

Interestingly, at least some of the research was publicly funded according to the news release,

Funding from the National Science Foundation, the Army Research Office and the Air Force supported their work.

Will the public ever benefit financially from this research?

Boosting chip speeds with graphene

There’s a certain hysteria associated with chip speeds as engineers and computer scientists try to achieve the ever improved speed times that consumers have enjoyed for some decades. The question looms, is there some point at which we can no longer improve the speed? Well, we haven’t reached that point yet according to a June 18, 2015 news item on Nanotechnology Now,

Stanford engineers find a simple yet clever way to boost chip speeds: Inside each chip are millions of tiny wires to transport data; wrapping them in a protective layer of graphene could boost speeds by up to 30 percent. [emphasis mine]

A June 16, 2015 Stanford University news release by Tom Abate (also on EurekAlert but dated June 17, 2015), which originated the news item, describes how computer chips are currently designed and the redesign which yields more speed,

A typical computer chip includes millions of transistors connected with an extensive network of copper wires. Although chip wires are unimaginably short and thin compared to household wires both have one thing in common: in each case the copper is wrapped within a protective sheath.

For years a material called tantalum nitride has formed protective layer in chip wires.

Now Stanford-led experiments demonstrate that a different sheathing material, graphene, can help electrons scoot through tiny copper wires in chips more quickly.

Graphene is a single layer of carbon atoms arranged in a strong yet thin lattice. Stanford electrical engineer H.-S. Philip Wong says this modest fix, using graphene to wrap wires, could allow transistors to exchange data faster than is currently possible. And the advantages of using graphene would become greater in the future as transistors continue to shrink.

Wong led a team of six researchers, including two from the University of Wisconsin-Madison, who will present their findings at the Symposia of VLSI Technology and Circuits in Kyoto, a leading venue for the electronics industry.

Ling Li, a graduate student in electrical engineering at Stanford and first author of the research paper, explained why changing the exterior wrapper on connecting wires can have such a big impact on chip performance.

It begins with understanding the dual role of this protective layer: it isolates the copper from the silicon on the chip and also serve to conduct electricity.

On silicon chips, the transistors act like tiny gates to switch electrons on or off. That switching function is how transistors process data.

The copper wires between the transistors transport this data once it is processed.

The isolating material–currently tantalum nitride–keeps the copper from migrating into the silicon transistors and rendering them non-functional.

Why switch to graphene?

Two reasons, starting with the ceaseless desire to keep making electronic components smaller.

When the Stanford team used the thinnest possible layer of tantalum nitride needed to perform this isolating function, they found that the industry-standard was eight times thicker than the graphene layer that did the same work.

Graphene had a second advantage as a protective sheathing and here it’s important to differentiate how this outer layer functions in chip wires versus a household wires.

In house wires the outer layer insulates the copper to prevent electrocution or fires.

In a chip the layer around the wires is a barrier to prevent copper atoms from infiltrating the silicon. Were that to happen the transistors would cease to function. So the protective layer isolates the copper from the silicon

The Stanford experiment showed that graphene could perform this isolating role while also serving as an auxiliary conductor of electrons. Its lattice structure allows electrons to leap from carbon atom to carbon atom straight down the wire, while effectively containing the copper atoms within the copper wire.

These benefits–the thinness of the graphene layer and its dual role as isolator and auxiliary conductor–allow this new wire technology to carry more data between transistors, speeding up overall chip performance in the process.

In today’s chips the benefits are modest; a graphene isolator would boost wire speeds from four percent to 17 percent, depending on the length of the wire. [emphasis mine]

But as transistors and wires continue to shrink in size, the benefits of the ultrathin yet conductive graphene isolator become greater. [emphasis mine] The Stanford engineers estimate that their technology could increase wire speeds by 30 percent in the next two generations

The Stanford researchers think the promise of faster computing will induce other researchers to get interested in wires, and help to overcome some of the hurdles needed to take this proof of principle into common practice.

This would include techniques to grow graphene, especially growing it directly onto wires while chips are being mass-produced. In addition to his University of Wisconsin collaborator Professor Michael Arnold, Wong cited Purdue University Professor Zhihong Chen. Wong noted that the idea of using graphene as an isolator was inspired by Cornell University Professor Paul McEuen and his pioneering research on the basic properties of this marvelous material. Alexander Balandin of the University of California-Riverside has also made contributions to using graphene in chips.

“Graphene has been promised to benefit the electronics industry for a long time, and using it as a copper barrier is perhaps the first realization of this promise,” Wong said.

I gather they’ve decided to highlight the most optimistic outcomes.