Tag Archives: Paul McEuen

An exoskeleton for a cell-sized robot

A January 3, 2018 news item on phys.org announces work on cell-sized robots,

An electricity-conducting, environment-sensing, shape-changing machine the size of a human cell? Is that even possible?

Cornell physicists Paul McEuen and Itai Cohen not only say yes, but they’ve actually built the “muscle” for one.

With postdoctoral researcher Marc Miskin at the helm, the team has made a robot exoskeleton that can rapidly change its shape upon sensing chemical or thermal changes in its environment. And, they claim, these microscale machines – equipped with electronic, photonic and chemical payloads – could become a powerful platform for robotics at the size scale of biological microorganisms.

“You could put the computational power of the spaceship Voyager onto an object the size of a cell,” Cohen said. “Then, where do you go explore?”

“We are trying to build what you might call an ‘exoskeleton’ for electronics,” said McEuen, the John A. Newman Professor of Physical Science and director of the Kavli Institute at Cornell for Nanoscale Science. “Right now, you can make little computer chips that do a lot of information-processing … but they don’t know how to move or cause something to bend.”

Cornell University has produced a video of the researchers discussing their work (about 3 mins. running time)

For those who prefer text or need it to reinforce their understanding, there’s a January 2, 2018 Cornell University news release (also on EurekAlert but dated Jan. 3, 2018) by Tom Fleischman, which originated the news item,

The machines move using a motor called a bimorph. A bimorph is an assembly of two materials – in this case, graphene and glass – that bends when driven by a stimulus like heat, a chemical reaction or an applied voltage. The shape change happens because, in the case of heat, two materials with different thermal responses expand by different amounts over the same temperature change.

As a consequence, the bimorph bends to relieve some of this strain, allowing one layer to stretch out longer than the other. By adding rigid flat panels that cannot be bent by bimorphs, the researchers localize bending to take place only in specific places, creating folds. With this concept, they are able to make a variety of folding structures ranging from tetrahedra (triangular pyramids) to cubes.

In the case of graphene and glass, the bimorphs also fold in response to chemical stimuli by driving large ions into the glass, causing it to expand. Typically this chemical activity only occurs on the very outer edge of glass when submerged in water or some other ionic fluid. Since their bimorph is only a few nanometers thick, the glass is basically all outer edge and very reactive.

“It’s a neat trick,” Miskin said, “because it’s something you can do only with these nanoscale systems.”

The bimorph is built using atomic layer deposition – chemically “painting” atomically thin layers of silicon dioxide onto aluminum over a cover slip – then wet-transferring a single atomic layer of graphene on top of the stack. The result is the thinnest bimorph ever made. One of their machines was described as being “three times larger than a red blood cell and three times smaller than a large neuron” when folded. Folding scaffolds of this size have been built before, but this group’s version has one clear advantage.

“Our devices are compatible with semiconductor manufacturing,” Cohen said. “That’s what’s making this compatible with our future vision for robotics at this scale.”

And due to graphene’s relative strength, Miskin said, it can handle the types of loads necessary for electronics applications. “If you want to build this electronics exoskeleton,” he said, “you need it to be able to produce enough force to carry the electronics. Ours does that.”

For now, these tiniest of tiny machines have no commercial application in electronics, biological sensing or anything else. But the research pushes the science of nanoscale robots forward, McEuen said.

“Right now, there are no ‘muscles’ for small-scale machines,” he said, “so we’re building the small-scale muscles.”

Here’s a link to and a citation for the paper,

Graphene-based bimorphs for micron-sized, autonomous origami machines by Marc Z. Miskin, Kyle J. Dorsey, Baris Bircan, Yimo Han, David A. Muller, Paul L. McEuen, and Itai Cohen. PNAS [Proceedings of the National Academy of Sciences] 2018 doi: 10.1073/pnas.1712889115 published ahead of print January 2, 2018

This paper is behind a paywall.

Boosting chip speeds with graphene

There’s a certain hysteria associated with chip speeds as engineers and computer scientists try to achieve the ever improved speed times that consumers have enjoyed for some decades. The question looms, is there some point at which we can no longer improve the speed? Well, we haven’t reached that point yet according to a June 18, 2015 news item on Nanotechnology Now,

Stanford engineers find a simple yet clever way to boost chip speeds: Inside each chip are millions of tiny wires to transport data; wrapping them in a protective layer of graphene could boost speeds by up to 30 percent. [emphasis mine]

A June 16, 2015 Stanford University news release by Tom Abate (also on EurekAlert but dated June 17, 2015), which originated the news item, describes how computer chips are currently designed and the redesign which yields more speed,

A typical computer chip includes millions of transistors connected with an extensive network of copper wires. Although chip wires are unimaginably short and thin compared to household wires both have one thing in common: in each case the copper is wrapped within a protective sheath.

For years a material called tantalum nitride has formed protective layer in chip wires.

Now Stanford-led experiments demonstrate that a different sheathing material, graphene, can help electrons scoot through tiny copper wires in chips more quickly.

Graphene is a single layer of carbon atoms arranged in a strong yet thin lattice. Stanford electrical engineer H.-S. Philip Wong says this modest fix, using graphene to wrap wires, could allow transistors to exchange data faster than is currently possible. And the advantages of using graphene would become greater in the future as transistors continue to shrink.

Wong led a team of six researchers, including two from the University of Wisconsin-Madison, who will present their findings at the Symposia of VLSI Technology and Circuits in Kyoto, a leading venue for the electronics industry.

Ling Li, a graduate student in electrical engineering at Stanford and first author of the research paper, explained why changing the exterior wrapper on connecting wires can have such a big impact on chip performance.

It begins with understanding the dual role of this protective layer: it isolates the copper from the silicon on the chip and also serve to conduct electricity.

On silicon chips, the transistors act like tiny gates to switch electrons on or off. That switching function is how transistors process data.

The copper wires between the transistors transport this data once it is processed.

The isolating material–currently tantalum nitride–keeps the copper from migrating into the silicon transistors and rendering them non-functional.

Why switch to graphene?

Two reasons, starting with the ceaseless desire to keep making electronic components smaller.

When the Stanford team used the thinnest possible layer of tantalum nitride needed to perform this isolating function, they found that the industry-standard was eight times thicker than the graphene layer that did the same work.

Graphene had a second advantage as a protective sheathing and here it’s important to differentiate how this outer layer functions in chip wires versus a household wires.

In house wires the outer layer insulates the copper to prevent electrocution or fires.

In a chip the layer around the wires is a barrier to prevent copper atoms from infiltrating the silicon. Were that to happen the transistors would cease to function. So the protective layer isolates the copper from the silicon

The Stanford experiment showed that graphene could perform this isolating role while also serving as an auxiliary conductor of electrons. Its lattice structure allows electrons to leap from carbon atom to carbon atom straight down the wire, while effectively containing the copper atoms within the copper wire.

These benefits–the thinness of the graphene layer and its dual role as isolator and auxiliary conductor–allow this new wire technology to carry more data between transistors, speeding up overall chip performance in the process.

In today’s chips the benefits are modest; a graphene isolator would boost wire speeds from four percent to 17 percent, depending on the length of the wire. [emphasis mine]

But as transistors and wires continue to shrink in size, the benefits of the ultrathin yet conductive graphene isolator become greater. [emphasis mine] The Stanford engineers estimate that their technology could increase wire speeds by 30 percent in the next two generations

The Stanford researchers think the promise of faster computing will induce other researchers to get interested in wires, and help to overcome some of the hurdles needed to take this proof of principle into common practice.

This would include techniques to grow graphene, especially growing it directly onto wires while chips are being mass-produced. In addition to his University of Wisconsin collaborator Professor Michael Arnold, Wong cited Purdue University Professor Zhihong Chen. Wong noted that the idea of using graphene as an isolator was inspired by Cornell University Professor Paul McEuen and his pioneering research on the basic properties of this marvelous material. Alexander Balandin of the University of California-Riverside has also made contributions to using graphene in chips.

“Graphene has been promised to benefit the electronics industry for a long time, and using it as a copper barrier is perhaps the first realization of this promise,” Wong said.

I gather they’ve decided to highlight the most optimistic outcomes.