Tag Archives: semiconductors

Bringing memristors to the masses and cutting down on energy use

One of my earliest posts featuring memristors (May 9, 2008) focused on their potential for energy savings but since then most of my postings feature research into their application in the field of neuromorphic (brainlike) computing. (For a description and abbreviated history of the memristor go to this page on my Nanotech Mysteries Wiki.)

In a sense this July 30, 2018 news item on Nanowerk is a return to the beginning,

A new way of arranging advanced computer components called memristors on a chip could enable them to be used for general computing, which could cut energy consumption by a factor of 100.

This would improve performance in low power environments such as smartphones or make for more efficient supercomputers, says a University of Michigan researcher.

“Historically, the semiconductor industry has improved performance by making devices faster. But although the processors and memories are very fast, they can’t be efficient because they have to wait for data to come in and out,” said Wei Lu, U-M professor of electrical and computer engineering and co-founder of memristor startup Crossbar Inc.

Memristors might be the answer. Named as a portmanteau of memory and resistor, they can be programmed to have different resistance states–meaning they store information as resistance levels. These circuit elements enable memory and processing in the same device, cutting out the data transfer bottleneck experienced by conventional computers in which the memory is separate from the processor.

A July 30, 2018 University of Michigan news release (also on EurekAlert), which originated the news item, expands on the theme,

… unlike ordinary bits, which are 1 or 0, memristors can have resistances that are on a continuum. Some applications, such as computing that mimics the brain (neuromorphic), take advantage of the analog nature of memristors. But for ordinary computing, trying to differentiate among small variations in the current passing through a memristor device is not precise enough for numerical calculations.

Lu and his colleagues got around this problem by digitizing the current outputs—defining current ranges as specific bit values (i.e., 0 or 1). The team was also able to map large mathematical problems into smaller blocks within the array, improving the efficiency and flexibility of the system.

Computers with these new blocks, which the researchers call “memory-processing units,” could be particularly useful for implementing machine learning and artificial intelligence algorithms. They are also well suited to tasks that are based on matrix operations, such as simulations used for weather prediction. The simplest mathematical matrices, akin to tables with rows and columns of numbers, can map directly onto the grid of memristors.

The memristor array situated on a circuit board.

The memristor array situated on a circuit board. Credit: Mohammed Zidan, Nanoelectronics group, University of Michigan.

Once the memristors are set to represent the numbers, operations that multiply and sum the rows and columns can be taken care of simultaneously, with a set of voltage pulses along the rows. The current measured at the end of each column contains the answers. A typical processor, in contrast, would have to read the value from each cell of the matrix, perform multiplication, and then sum up each column in series.

“We get the multiplication and addition in one step. It’s taken care of through physical laws. We don’t need to manually multiply and sum in a processor,” Lu said.

His team chose to solve partial differential equations as a test for a 32×32 memristor array—which Lu imagines as just one block of a future system. These equations, including those behind weather forecasting, underpin many problems science and engineering but are very challenging to solve. The difficulty comes from the complicated forms and multiple variables needed to model physical phenomena.

When solving partial differential equations exactly is impossible, solving them approximately can require supercomputers. These problems often involve very large matrices of data, so the memory-processor communication bottleneck is neatly solved with a memristor array. The equations Lu’s team used in their demonstration simulated a plasma reactor, such as those used for integrated circuit fabrication.

This work is described in a study, “A general memristor-based partial differential equation solver,” published in the journal Nature Electronics.

It was supported by the Defense Advanced Research Projects Agency (DARPA) (grant no. HR0011-17-2-0018) and by the National Science Foundation (NSF) (grant no. CCF-1617315).

Here’s a link and a citation for the paper,

A general memristor-based partial differential equation solver by Mohammed A. Zidan, YeonJoo Jeong, Jihang Lee, Bing Chen, Shuo Huang, Mark J. Kushner & Wei D. Lu. Nature Electronicsvolume 1, pages411–420 (2018) DOI: https://doi.org/10.1038/s41928-018-0100-6 Published: 13 July 2018

This paper is behind a paywall.

For the curious, Dr. Lu’s startup company, Crossbar can be found here.

The mystifying physics of paint-on semiconductors

I was not expecting a Canadian connection but it seems we are heavily invested in this research at the Georgia Institute of Technology (Georgia Tech), from a March 19, 2018 news item on ScienceDaily,

Some novel materials that sound too good to be true turn out to be true and good. An emergent class of semiconductors, which could affordably light up our future with nuanced colors emanating from lasers, lamps, and even window glass, could be the latest example.

These materials are very radiant, easy to process from solution, and energy-efficient. The nagging question of whether hybrid organic-inorganic perovskites (HOIPs) could really work just received a very affirmative answer in a new international study led by physical chemists at the Georgia Institute of Technology.

A March 19,. 2018 Georgia Tech news release (also on EurekAlert), which originated the news item, provides more detail,

The researchers observed in an HOIP a “richness” of semiconducting physics created by what could be described as electrons dancing on chemical underpinnings that wobble like a funhouse floor in an earthquake. That bucks conventional wisdom because established semiconductors rely upon rigidly stable chemical foundations, that is to say, quieter molecular frameworks, to produce the desired quantum properties.

“We don’t know yet how it works to have these stable quantum properties in this intense molecular motion,” said first author Felix Thouin, a graduate research assistant at Georgia Tech. “It defies physics models we have to try to explain it. It’s like we need some new physics.”

Quantum properties surprise

Their gyrating jumbles have made HOIPs challenging to examine, but the team of researchers from a total of five research institutes in four countries succeeded in measuring a prototypical HOIP and found its quantum properties on par with those of established, molecularly rigid semiconductors, many of which are graphene-based.

“The properties were at least as good as in those materials and may be even better,” said Carlos Silva, a professor in Georgia Tech’s School of Chemistry and Biochemistry. Not all semiconductors also absorb and emit light well, but HOIPs do, making them optoelectronic and thus potentially useful in lasers, LEDs, other lighting applications, and also in photovoltaics.

The lack of molecular-level rigidity in HOIPs also plays into them being more flexibly produced and applied.

Silva co-led the study with physicist Ajay Ram Srimath Kandada. Their team published the results of their study on two-dimensional HOIPs on March 8, 2018, in the journal Physical Review Materials. Their research was funded by EU Horizon 2020, the Natural Sciences and Engineering Research Council of Canada, the Fond Québécois pour la Recherche, the [National] Research Council of Canada, and the National Research Foundation of Singapore. [emphases mine]

The ‘solution solution’

Commonly, semiconducting properties arise from static crystalline lattices of neatly interconnected atoms. In silicon, for example, which is used in most commercial solar cells, they are interconnected silicon atoms. The same principle applies to graphene-like semiconductors.

“These lattices are structurally not very complex,” Silva said. “They’re only one atom thin, and they have strict two-dimensional properties, so they’re much more rigid.”

“You forcefully limit these systems to two dimensions,” said Srimath Kandada, who is a Marie Curie International Fellow at Georgia Tech and the Italian Institute of Technology. “The atoms are arranged in infinitely expansive, flat sheets, and then these very interesting and desirable optoelectronic properties emerge.”

These proven materials impress. So, why pursue HOIPs, except to explore their baffling physics? Because they may be more practical in important ways.

“One of the compelling advantages is that they’re all made using low-temperature processing from solutions,” Silva said. “It takes much less energy to make them.”

By contrast, graphene-based materials are produced at high temperatures in small amounts that can be tedious to work with. “With this stuff (HOIPs), you can make big batches in solution and coat a whole window with it if you want to,” Silva said.

Funhouse in an earthquake

For all an HOIP’s wobbling, it’s also a very ordered lattice with its own kind of rigidity, though less limiting than in the customary two-dimensional materials.

“It’s not just a single layer,” Srimath Kandada said. “There is a very specific perovskite-like geometry.” Perovskite refers to the shape of an HOIPs crystal lattice, which is a layered scaffolding.

“The lattice self-assembles,” Srimath Kandada said, “and it does so in a three-dimensional stack made of layers of two-dimensional sheets. But HOIPs still preserve those desirable 2D quantum properties.”

Those sheets are held together by interspersed layers of another molecular structure that is a bit like a sheet of rubber bands. That makes the scaffolding wiggle like a funhouse floor.

“At room temperature, the molecules wiggle all over the place. That disrupts the lattice, which is where the electrons live. It’s really intense,” Silva said. “But surprisingly, the quantum properties are still really stable.”

Having quantum properties work at room temperature without requiring ultra-cooling is important for practical use as a semiconductor.

Going back to what HOIP stands for — hybrid organic-inorganic perovskites – this is how the experimental material fit into the HOIP chemical class: It was a hybrid of inorganic layers of a lead iodide (the rigid part) separated by organic layers (the rubber band-like parts) of phenylethylammonium (chemical formula (PEA)2PbI4).

The lead in this prototypical material could be swapped out for a metal safer for humans to handle before the development of an applicable material.

Electron choreography

HOIPs are great semiconductors because their electrons do an acrobatic square dance.

Usually, electrons live in an orbit around the nucleus of an atom or are shared by atoms in a chemical bond. But HOIP chemical lattices, like all semiconductors, are configured to share electrons more broadly.

Energy levels in a system can free the electrons to run around and participate in things like the flow of electricity and heat. The orbits, which are then empty, are called electron holes, and they want the electrons back.

“The hole is thought of as a positive charge, and of course, the electron has a negative charge,” Silva said. “So, hole and electron attract each other.”

The electrons and holes race around each other like dance partners pairing up to what physicists call an “exciton.” Excitons act and look a lot like particles themselves, though they’re not really particles.

Hopping biexciton light

In semiconductors, millions of excitons are correlated, or choreographed, with each other, which makes for desirable properties, when an energy source like electricity or laser light is applied. Additionally, excitons can pair up to form biexcitons, boosting the semiconductor’s energetic properties.

“In this material, we found that the biexciton binding energies were high,” Silva said. “That’s why we want to put this into lasers because the energy you input ends up to 80 or 90 percent as biexcitons.”

Biexcitons bump up energetically to absorb input energy. Then they contract energetically and pump out light. That would work not only in lasers but also in LEDs or other surfaces using the optoelectronic material.

“You can adjust the chemistry (of HOIPs) to control the width between biexciton states, and that controls the wavelength of the light given off,” Silva said. “And the adjustment can be very fine to give you any wavelength of light.”

That translates into any color of light the heart desires.

###

Coauthors of this paper were Stefanie Neutzner and Annamaria Petrozza from the Italian Institute of Technology (IIT); Daniele Cortecchia from IIT and Nanyang Technological University (NTU), Singapore; Cesare Soci from the Centre for Disruptive Photonic Technologies, Singapore; Teddy Salim and Yeng Ming Lam from NTU; and Vlad Dragomir and Richard Leonelli from the University of Montreal. …

Three Canadian science funding agencies plus European and Singaporean science funding agencies but not one from the US ? That’s a bit unusual for research undertaken at a US educational institution.

In any event, here’s a link to and a citation for the paper,

Stable biexcitons in two-dimensional metal-halide perovskites with strong dynamic lattice disorder by Félix Thouin, Stefanie Neutzner, Daniele Cortecchia, Vlad Alexandru Dragomir, Cesare Soci, Teddy Salim, Yeng Ming Lam, Richard Leonelli, Annamaria Petrozza, Ajay Ram Srimath Kandada, and Carlos Silva. Phys. Rev. Materials 2, 034001 – Published 8 March 2018

This paper is behind a paywall.

Interstellar fullerenes

This work from Russia on fullerenes (also known as buckministerfullerenes, C60, and/or buckyballs) is quite interesting and dates back more than a year. I’m not sure why the work is being publicized now but nanotechnology and interstellar space is not covered here often enough so, here goes, (from a January 29, 2018 Kazan Federal University press release (also on EurekAlert), Note: Links have been removed,

Here’s a link to and a citation for the paper,

C60+ – looking for the bucky-ball in interstellar space by G. A. Galazutdinov, V. V. Shimansky, A. Bondar, G. Valyavin, J. Krełowski. Monthly Notices of the Royal Astronomical Society, Volume 465, Issue 4, 11 March 2017, Pages 3956–3964, https://doi.org/10.1093/mnras/stw2948 Published: 22 December 2016

This paper is behind a paywall.

h/t January 29, 2018 news item on Nanowerk

Cyborg bacteria to reduce carbon dioxide

This video is a bit technical but then it is about work being presented to chemists at the American Chemical Society’s (ACS) at the 254th National Meeting & Exposition Aug. 20 -24, 2017,

For a more plain language explanation, there’s an August 22, 2017 ACS news release (also on EurekAlert),

Photosynthesis provides energy for the vast majority of life on Earth. But chlorophyll, the green pigment that plants use to harvest sunlight, is relatively inefficient. To enable humans to capture more of the sun’s energy than natural photosynthesis can, scientists have taught bacteria to cover themselves in tiny, highly efficient solar panels to produce useful compounds.

“Rather than rely on inefficient chlorophyll to harvest sunlight, I’ve taught bacteria how to grow and cover their bodies with tiny semiconductor nanocrystals,” says Kelsey K. Sakimoto, Ph.D., who carried out the research in the lab of Peidong Yang, Ph.D. “These nanocrystals are much more efficient than chlorophyll and can be grown at a fraction of the cost of manufactured solar panels.”

Humans increasingly are looking to find alternatives to fossil fuels as sources of energy and feedstocks for chemical production. Many scientists have worked to create artificial photosynthetic systems to generate renewable energy and simple organic chemicals using sunlight. Progress has been made, but the systems are not efficient enough for commercial production of fuels and feedstocks.

Research in Yang’s lab at the University of California, Berkeley, where Sakimoto earned his Ph.D., focuses on harnessing inorganic semiconductors that can capture sunlight to organisms such as bacteria that can then use the energy to produce useful chemicals from carbon dioxide and water. “The thrust of research in my lab is to essentially ‘supercharge’ nonphotosynthetic bacteria by providing them energy in the form of electrons from inorganic semiconductors, like cadmium sulfide, that are efficient light absorbers,” Yang says. “We are now looking for more benign light absorbers than cadmium sulfide to provide bacteria with energy from light.”

Sakimoto worked with a naturally occurring, nonphotosynthetic bacterium, Moorella thermoacetica, which, as part of its normal respiration, produces acetic acid from carbon dioxide (CO2). Acetic acid is a versatile chemical that can be readily upgraded to a number of fuels, polymers, pharmaceuticals and commodity chemicals through complementary, genetically engineered bacteria.

When Sakimoto fed cadmium and the amino acid cysteine, which contains a sulfur atom, to the bacteria, they synthesized cadmium sulfide (CdS) nanoparticles, which function as solar panels on their surfaces. The hybrid organism, M. thermoacetica-CdS, produces acetic acid from CO2, water and light. “Once covered with these tiny solar panels, the bacteria can synthesize food, fuels and plastics, all using solar energy,” Sakimoto says. “These bacteria outperform natural photosynthesis.”

The bacteria operate at an efficiency of more than 80 percent, and the process is self-replicating and self-regenerating, making this a zero-waste technology. “Synthetic biology and the ability to expand the product scope of CO2 reduction will be crucial to poising this technology as a replacement, or one of many replacements, for the petrochemical industry,” Sakimoto says.

So, do the inorganic-biological hybrids have commercial potential? “I sure hope so!” he says. “Many current systems in artificial photosynthesis require solid electrodes, which is a huge cost. Our algal biofuels are much more attractive, as the whole CO2-to-chemical apparatus is self-contained and only requires a big vat out in the sun.” But he points out that the system still requires some tweaking to tune both the semiconductor and the bacteria. He also suggests that it is possible that the hybrid bacteria he created may have some naturally occurring analog. “A future direction, if this phenomenon exists in nature, would be to bioprospect for these organisms and put them to use,” he says.

For more insight into the work, check out Dexter Johnson’s Aug. 22, 2017 posting on his Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website),

“It’s actually a natural, overlooked feature of their biology,” explains Sakimoto in an e-mail interview with IEEE Spectrum. “This bacterium has a detoxification pathway, meaning if it encounters a toxic metal, like cadmium, it will try to precipitate it out, thereby detoxifying it. So when we introduce cadmium ions into the growth medium in which M. thermoacetica is hanging out, it will convert the amino acid cysteine into sulfide, which precipitates out cadmium as cadmium sulfide. The crystals then assemble and stick onto the bacterium through normal electrostatic interactions.”

I’ve just excerpted one bit, there’s more in Dexter’s posting.

IBM and a 5 nanometre chip

If this continues, they’re going to have change the scale from nano to pico. IBM has announced work on a 5 nanometre (5nm) chip in a June 5, 2017 news item on Nanotechnology Now,

IBM (NYSE: IBM), its Research Alliance partners GLOBALFOUNDRIES and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

A June 5, 2017 IBM news release, which originated the news item, spells out some of the details about IBM’s latest breakthrough,

The resulting increase in performance will help accelerate cognitive computing [emphasis mine], the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.”

The silicon nanosheet transistor demonstration, as detailed in the Research Alliance paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, and published by VLSI, proves that 5nm chips are possible, more powerful, and not too far off in the future.

Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

Building a New Switch

“This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in New York,” said Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”

IBM Research has explored nanosheet semiconductor technology for more than 10 years. This work is the first in the industry to demonstrate the feasibility to design and fabricate stacked nanosheet devices with electrical properties superior to FinFET architecture.

This same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node and its 20 billion transistors was applied to the nanosheet transistor architecture. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.

“Today’s announcement continues the public-private model collaboration with IBM that is energizing SUNY-Polytechnic’s, Albany’s, and New York State’s leadership and innovation in developing next generation technologies,” said Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute. “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities. SUNY Poly’s partnership with IBM and Empire State Development is a perfect example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society.”

Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), the proof of nanosheet architecture scaling to a 5nm node continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

I last wrote about IBM and computer chips in a July 15, 2015 posting regarding their 7nm chip. You may want to scroll down approximately 55% of the way where I note research from MIT (Massachusetts Institute of Technology) about metal nanoparticles with unexpected properties possibly having an impact on nanoelectronics.

Getting back to IBM, they have produced a slick video about their 5nm chip breakthrough,

Meanwhile, Katherine Bourzac provides technical detail in a June 5, 2017 posting on the Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website), Note: A link has been removed,

Researchers at IBM believe the future of the transistor is in stacked nanosheets. …

Today’s state-of-the-art transistor is the finFET, named for the fin-like ridges of current-carrying silicon that project from the chip’s surface. The silicon fins are surrounded on their three exposed sides by a structure called the gate. The gate switches the flow of current on, and prevents electrons from leaking out when the transistor is off. This design is expected to last from this year’s bleeding-edge process technology, the “10-nanometer” node, through the next node, 7 nanometers. But any smaller, and these transistors will become difficult to switch off: electrons will leak out, even with the three-sided gates.

So the semiconductor industry has been working on alternatives for the upcoming 5 nanometer node. One popular idea is to use lateral silicon nanowires that are completely surrounded by the gate, preventing electron leaks and saving power. This design is called “gate all around.” IBM’s new design is a variation on this. In their test chips, each transistor is made up of three stacked horizontal sheets of silicon, each only a few nanometers thick and completely surrounded by a gate.

Why a sheet instead of a wire? Huiming Bu, director of silicon integration and devices at IBM, says nanosheets can bring back one of the benefits of pre-finFET, planar designs. Designers used to be able to vary the width of a transistor to prioritize fast operations or energy efficiency. Varying the amount of silicon in a finFET transistor is not practicable because it would mean making some fins taller and other shorter. Fins must all be the same height due to manufacturing constraints, says Bu.

IBM’s nanosheets can range from 8 to 50 nanometers in width. “Wider gives you better performance but takes more power, smaller width relaxes performance but reduces power use,” says Bu. This will allow circuit designers to pick and choose what they need, whether they are making a power efficient mobile chip processor or designing a bank of SRAM memory. “We are bringing flexibility back to the designers,” he says.

The test chips have 30 billion transistors. …

It was a struggle trying to edit Bourzac’s posting with its good detail and clear writing. I encourage you to read it (June 5, 2017 posting) in its entirety.

As for where this drive downwards to the ‘ever smaller’ is going, there’s Dexter’s Johnson’s June 29, 2017 posting about another IBM team’s research on his Nanoclast blog on the IEEE website (Note: Links have been removed),

There have been increasing signs coming from the research community that carbon nanotubes are beginning to step up to the challenge of offering a real alternative to silicon-based complementary metal-oxide semiconductor (CMOS) transistors.

Now, researchers at IBM Thomas J. Watson Research Center have advanced carbon nanotube-based transistors another step toward meeting the demands of the International Technology Roadmap for Semiconductors (ITRS) for the next decade. The IBM researchers have fabricated a p-channel transistor based on carbon nanotubes that takes up less than half the space of leading silicon technologies while operating at a lower voltage.

In research described in the journal Science, the IBM scientists used a carbon nanotube p-channel to reduce the transistor footprint; their transistor contains all components to 40 square nanometers [emphasis mine], an ITRS roadmap benchmark for ten years out.

One of the keys to being able to reduce the transistor to such a small size is the use of the carbon nanotube as the channel in place of silicon. The nanotube is only 1 nanometer thick. Such thinness offers a significant advantage in electrostatics, so that it’s possible to reduce the device gate length to 10 nanometers without seeing the device performance adversely affected by short-channel effects. An additional benefit of the nanotubes is that the electrons travel much faster, which contributes to a higher level of device performance.

Happy reading!

A new type of diode from South Korea’s Ulsan National Institute of Science and Technology

A Feb. 8, 2017 news item on phys.org features a ‘dream’ diode from Ulsan National Institute of Science and Technology,

A team of researchers, affiliated with UNIST [Ulsan National Institute of Science and Technology] has created a new technique that greatly enhances the performance of Schottky Diodes (metal-semiconductor junction) used in electronic devices. Their research findings have attracted considerable attention within the scientific community by solving the contact resistance problem of metal-semiconductor, which had remained unsolved for almost 50 years.

As described in the January [2017] issue of Nano Letters, the researchers have created a new type of diode with a graphene insertion layer sandwiched between metal and semiconductor. This new technique blows all previous attemps out the water, as it is expected to significantly contribute to the semiconductor industry’s growth.

A Jan. 27, 2017 UNIST press release, (also on EurekAlert), which originated the news item, describes the research in greater detail,

The Schottky diode is one of the oldest and most representative semiconductor devices, formed by the junction of a semiconductor with a metal.  However, due to the atomic intermixing along the interface between two materials, it has been impossible to produce an ideal diode. (An ideal diode acts like a perfect conductor when voltage is applied forward biased and like a perfect insulator when voltage is applied reverse biased.)

graphene interlayer 2

The schematic view of internal photoemission (IPE) measurements on metal/n-Si(001) junctions with Ni, Pt, and Ti electrodes for with and without a graphene insertion layer.

Professor Kibog Park of Natural Science solved this problem by inserting a graphene layer at the metal-semiconductor interface. In the study, the research team demonstrated that this graphene layer, consisting of a single layer of carbon atoms can not only suppress the material intermixing substantially, but also matches well with the theoretical prediction.

“The sheets of graphene in graphite have a space between each sheet that shows a high electron density of quantum mechanics in that no atoms can pass through,” says Professor Park. “Therefore, with this single-layer graphene sandwiched between metal and semiconductor, it is possible to overcome the inevitable atomic diffusion problem.”

The study also has the physiological meaning of confirming the theoretical prediction that “In the case of silicon semiconductors, the electrical properties of the junction surfaces hardly change regardless of the type of metal they use,” according to Hoon Hahn Yoon (Combined M.S./Ph.D. student of Natural Science), the first author of the study.

The internal photoemission method was used to measure the electronic energy barrier of the newly-fabricated metal/graphene/n-Si(001) junction diodes. The Internal Photoemission (IPE) Measurement System in the image shown above has contributed greatly to these experiments. This system has been developed by four UNIST graduate students (Hoon Han Yoon, Sungchul Jung, Gahyun Choi, and Junhyung Kim), which was carried out as part of an undergraduate research project in 2012 and was supported by the Korea Foundation for the Advancement of Science and Creativity (KOFAC).

This is the internal photoemission (IPE) measurement system, developed by Hoon Hahn Yoon of Physics at UNIST.

Shown above is the Internal Photoemission (IPE) Measurement System, developed by Hoon Hahn Yoon, combined M.S./Ph.D. student of Natural Science at UNIST.

“Students have teamed up and carried out all the necessary steps for the research since they were undergraduates,” Professor Park says. “Therefore, this research is a perfect example of time, persistence, and patience paying off.”

This study has been jointly conducted by Professor Hu Young Jeong of the UNIST Central Research Facilities (UCRF), Professor Kwanpyo Kim of Natural Science, Professor Soon-Yong Kwon of Materials Science and Engineering, and Professor Yong Soo Kim of Ulsan University. It has been also supported by the National Research Foundation of Korea, Nuclear Research Basis Expansion Project, as well as the Global Ph.D Fellowship (GPF).

Here’s a link to and a citation for the paper,

Strong Fermi-Level Pinning at Metal/n-Si(001) Interface Ensured by Forming an Intact Schottky Contact with a Graphene Insertion Layer by Hoon Hahn Yoon, Sungchul Jung, Gahyun Choi, Junhyung Kim, Youngeun Jeon, Yong Soo Kim, Hu Young Jeong, Kwanpyo Kim, Soon-Yong Kwon, and Kibog Park. Nano Lett., 2017, 17 (1), pp 44–49 DOI: 10.1021/acs.nanolett.6b03137 Publication Date (Web): December 14, 2016

Copyright © 2016 American Chemical Society

This paper is behind a paywall.

Memory material with functions resembling synapses and neurons in the brain

This work comes from the University of Twente’s MESA+ Institute for Nanotechnology according to a July 8, 2016 news item on ScienceDaily,

Our brain does not work like a typical computer memory storing just ones and zeroes: thanks to a much larger variation in memory states, it can calculate faster consuming less energy. Scientists of the MESA+ Institute for Nanotechnology of the University of Twente (The Netherlands) now developed a ferro-electric material with a memory function resembling synapses and neurons in the brain, resulting in a multistate memory. …

A July 8, 2016 University of Twente press release, which originated the news item, provides more technical detail,

The material that could be the basic building block for ‘brain-inspired computing’ is lead-zirconium-titanate (PZT): a sandwich of materials with several attractive properties. One of them is that it is ferro-electric: you can switch it to a desired state, this state remains stable after the electric field is gone. This is called polarization: it leads to a fast memory function that is non-volatile. Combined with processor chips, a computer could be designed that starts much faster, for example. The UT scientists now added a thin layer of zinc oxide to the PZT, 25 nanometer thickness. They discovered that switching from one state to another not only happens from ‘zero’ to ‘one’ vice versa. It is possible to control smaller areas within the crystal: will they be polarized (‘flip’) or not?

In a PZT layer without zinc oxide (ZnO) there are basically two memorystates. Adding a nano layer of ZnO, every state in between is possible as well.

Multistate

By using variable writing times in those smaller areas, the result is that many states can be stored anywhere between zero and one. This resembles the way synapses and neurons ‘weigh’ signals in our brain. Multistate memories, coupled to transistors, could drastically improve the speed of pattern recognition, for example: our brain performs this kind of tasks consuming only a fraction of the energy a computer system needs. Looking at the graphs, the writing times seem quite long compared to nowaday’s processor speeds, but it is possible to create many memories in parallel. The function of the brain has already been mimicked in software like neurale networks, but in that case conventional digital hardware is still a limitation. The new material is a first step towards electronic hardware with a brain-like memory. Finding solutions for combining PZT with semiconductors, or even developing new kinds of semiconductors for this, is one of the next steps.

Here’s a link to and a citation for the paper,

Multistability in Bistable Ferroelectric Materials toward Adaptive Applications by Anirban Ghosh, Gertjan Koster, and Guus Rijnders. Advanced Functional Materials DOI: 10.1002/adfm.201601353 Version of Record online: 4 JUL 2016

© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

This paper is behind a paywall.

Diamond-based electronics?

A May 24, 2016 news item on ScienceDaily describes the latest research on using diamonds as semiconductors,

Along with being a “girl’s best friend,” diamonds also have remarkable properties that could make them ideal semiconductors. This is welcome news for electronics; semiconductors are needed to meet the rising demand for more efficient electronics that deliver and convert power.

The thirst for electronics is unlikely to cease and almost every appliance or device requires a suite of electronics that transfer, convert and control power. Now, researchers have taken an important step toward that technology with a new way to dope single crystals of diamonds, a crucial process for building electronic devices.

A May 24, 2016 American Institute of Physics (AIP) news release (also on EurekAlert), which originated the news item, provides more detail,

For power electronics, diamonds could serve as the perfect material. They are thermally conductive, which means diamond-based devices would dissipate heat quickly and easily, foregoing the need for bulky and expensive methods for cooling. Diamond can also handle high voltages and power. Electrical currents also flow through diamonds quickly, meaning the material would make for energy efficient devices.

But among the biggest challenges to making diamond-based devices is doping, a process in which other elements are integrated into the semiconductor to change its properties. Because of diamond’s rigid crystalline structure, doping is difficult.

Currently, you can dope diamond by coating the crystal with boron and heating it to 1450 degrees Celsius. But it’s difficult to remove the boron coating at the end. This method only works on diamonds consisting of multiple crystals stuck together. Because such polydiamonds have irregularities between the crystals, single-crystals would be superior semiconductors.

You can dope single crystals by injecting boron atoms while growing the crystals artificially. The problem is the process requires powerful microwaves that can degrade the quality of the crystal.

Now, Ma [Zhengqiang (Jack) Ma, an electrical and computer engineering professor at the University of Wisconsin-Madison] and his colleagues have found a way to dope single-crystal diamonds with boron at relatively low temperatures and without any degradation. The researchers discovered if you bond a single-crystal diamond with a piece of silicon doped with boron, and heat it to 800 degrees Celsius, which is low compared to the conventional techniques, the boron atoms will migrate from the silicon to the diamond. It turns out that the boron-doped silicon has defects such as vacancies, where an atom is missing in the lattice structure. Carbon atoms from the diamond will fill those vacancies, leaving empty spots for boron atoms.

This technique also allows for selective doping, which means more control when making devices. You can choose where to dope a single-crystal diamond simply by bonding the silicon to that spot.

The new method only works for P-type doping, where the semiconductor is doped with an element that provides positive charge carriers (in this case, the absence of electrons, called holes).

“We feel like we found a very easy, inexpensive, and effective way to do it,” Ma said. The researchers are already working on a simple device using P-type single-crystal diamond semiconductors.

But to make electronic devices like transistors, you need N-type doping that gives the semiconductor negative charge carriers (electrons). And other barriers remain. Diamond is expensive and single crystals are very small.

Still, Ma says, achieving P-type doping is an important step, and might inspire others to find solutions for the remaining challenges. Eventually, he said, single-crystal diamond could be useful everywhere — perfect, for instance, for delivering power through the grid.

Here’s an image the researchers have released,

Optical image of a diode array on a natural single crystalline diamond plate. (The image looks blurred due to light scattering by the array of small pads on top of the diamond plate.) Inset shows the deposited anode metal on top of heavy doped Si nanomembrane that is bonded to natural single crystalline diamond. CREDIT: Jung-Hun Seo

Optical image of a diode array on a natural single crystalline diamond plate. (The image looks blurred due to light scattering by the array of small pads on top of the diamond plate.) Inset shows the deposited anode metal on top of heavy doped Si nanomembrane that is bonded to natural single crystalline diamond. CREDIT: Jung-Hun Seo Courtesy: American Institute of Physics

Here’s a link to and a citation for the paper,

Thermal diffusion boron doping of single-crystal natural diamond by Jung-Hun Seo, Henry Wu, Solomon Mikael, Hongyi Mi, James P. Blanchard, Giri Venkataramanan, Weidong Zhou, Shaoqin Gong, Dane Morgan, and Zhenqiang Ma. J. Appl. Phys. 119, 205703 (2016); http://dx.doi.org/10.1063/1.4949327

This paper appears to be open access.

How vibrations affect nanoscale materials

A March 9, 2016 news item on ScienceDaily announces work concerning atomic vibrations,

All materials are made up of atoms, which vibrate. These vibrations, or ‘phonons’, are responsible, for example, for how electric charge and heat is transported in materials. Vibrations of metals, semiconductors, and insulators in are well studied; however, now materials are being nanosized to bring better performance to applications such as displays, sensors, batteries, and catalytic membranes. What happens to vibrations when a material is nanosized has until now not been understood.

A March 9, 2016 ETH Zurich press release (also on EurekAlert), which originated the news item, describes the world of vibration at the nanoscale and the potential impact this new information could have,

Soft Surfaces Vibrate Strongly

In a recent publication in Nature, ETH Professor Vanessa Wood and her colleagues explain what happens to atomic vibrations when materials are nanosized and how this knowledge can be used to systematically engineer nanomaterials for different applications.

The paper shows that when materials are made smaller than about 10 to 20 nanometers – that is, 5,000 times thinner than a human air – the vibrations of the outermost atomic layers on surface of the nanoparticle are large and play an important role in how this material behaves.

“For some applications, like catalysis, thermoelectrics, or superconductivity, these large vibrations may be good, but for other applications like LEDs or solar cells, these vibrations are undesirable,” explains Wood.

Indeed, the paper explains why nanoparticle-based solar cells have until now not met their full promise.  The researchers showed using both experiment and theory that surface vibrations interact with electrons to reduce the photocurrent in solar cells.

“Now that we have proven that surface vibrations are important, we can systematically design materials to suppress or enhance these vibrations,” say Wood.

Improving Solar Cells

Wood’s research group has worked for a long time on a particular type of nanomaterial – colloidal nanocrystals – semiconductors with a diameter of 2 to 10 nanometers.  These materials are interesting because their optical and electrical properties are dependent on their size, which can be easily changed during their synthesis.

These materials are now used commercially as red- and green-light emitters in LED-based TVs and are being explored as possible materials for low cost, solution-processed solar cells.  Researchers have noticed that placing certain atoms around the surface of the nanocrystal can improve the performance of solar cells. The reason why this worked had not been understood.  The work published in the Nature paper now gives the answer:  a hard shell of atoms can suppress the vibrations and their interaction with electrons.  This means a higher photocurrent and a higher efficiency solar cell.

Big Science to Study the Nanoscale

Experiments were conducted in Professor Wood’s labs at ETH Zurich and at the Swiss Spallation Neutron Source at the Paul Scherrer Institute. By observing how neutrons scatter off atoms in a material, it is possible to quantify how atoms in a material vibrate. To understand the neutron measurements, simulations of the atomic vibrations were run at the Swiss National Supercomputing Center (CSCS) in Lugano. Wood says, “without access to these large facilities, this work would not have been possible. We are incredibly fortunate here in Switzerland to have these world class facilities.”

The researchers have made available an image illustrating their work,

Vibrations of atoms in materials, the "phonons", are responsible for how electric charge and heat is transported in materials (Graphics: Deniz Bozyigit / ETH Zurich)

Vibrations of atoms in materials, the “phonons”, are responsible for how electric charge and heat is transported in materials (Graphics: Deniz Bozyigit / ETH Zurich)

Here’s a link to and a citation for the paper,

Soft surfaces of nanomaterials enable strong phonon interactions by Deniz Bozyigit, Nuri Yazdani, Maksym Yarema, Olesya Yarema, Weyde Matteo Mario Lin, Sebastian Volk, Kantawong Vuttivorakulchai, Mathieu Luisier, Fanni Juranyi, & Vanessa Wood. Nature (2016)  doi:10.1038/nature16977 Published online 09 March 2016

This paper is behind a paywall.

IBM, the Cognitive Era, and carbon nanotube electronics

IBM has a storied position in the field of nanotechnology due to the scanning tunneling microscope developed in the company’s laboratories. It was a Nobel Prize-winning breakthough which provided the impetus for nanotechnology applied research. Now, an Oct. 1, 2015 news item on Nanowerk trumpets another IBM breakthrough,

IBM Research today [Oct. 1, 2015] announced a major engineering breakthrough that could accelerate carbon nanotubes replacing silicon transistors to power future computing technologies.

IBM scientists demonstrated a new way to shrink transistor contacts without reducing performance of carbon nanotube devices, opening a pathway to dramatically faster, smaller and more powerful computer chips beyond the capabilities of traditional semiconductors.

While the Oct. 1, 2015 IBM news release, which originated the news item, does go on at length there’s not much technical detail (see the second to last paragraph in the excerpt for the little they do include) about the research breakthrough (Note: Links have been removed),

IBM’s breakthrough overcomes a major hurdle that silicon and any semiconductor transistor technologies face when scaling down. In any transistor, two things scale: the channel and its two contacts. As devices become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now. These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away. [emphasis mine]

Carbon nanotube chips could greatly improve the capabilities of high performance computers, enabling Big Data to be analyzed faster, increasing the power and battery life of mobile devices and the Internet of Things, and allowing cloud data centers to deliver services more efficiently and economically.

Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. With Moore’s Law running out of steam, shrinking the size of the transistor – including the channels and contacts – without compromising performance has been a vexing challenge troubling researchers for decades.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology. IBM’s new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip [emphasis mine], pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry. By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

“These chip innovations are necessary to meet the emerging demands of cloud computing, Internet of Things and Big Data systems,” said Dario Gil, vice president of Science & Technology at IBM Research. “As silicon technology nears its physical limits, new materials, devices and circuit architectures must be ready to deliver the advanced technologies that will be required by the Cognitive Computing era. This breakthrough shows that computer chips made of carbon nanotubes will be able to power systems of the future sooner than the industry expected.”

A New Contact for Carbon Nanotubes

Carbon nanotubes represent a new class of semiconductor materials that consist of single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device whose superior electrical properties promise several generations of technology scaling beyond the physical limits of silicon.

Electrons in carbon transistors can move more easily than in silicon-based devices, and the ultra-thin body of carbon nanotubes provide additional advantages at the atomic scale. Inside a chip, contacts are the valves that control the flow of electrons from metal into the channels of a semiconductor. As transistors shrink in size, electrical resistance increases within the contacts, which impedes performance. Until now, decreasing the size of the contacts on a device caused a commensurate drop in performance – a challenge facing both silicon and carbon nanotube transistor technologies.

IBM researchers had to forego traditional contact schemes and invented a metallurgical process akin to microscopic welding that chemically binds the metal atoms to the carbon atoms at the ends of nanotubes. This ‘end-bonded contact scheme’ allows the contacts to be shrunken down to below 10 nanometers without deteriorating performance of the carbon nanotube devices.

“For any advanced transistor technology, the increase in contact resistance due to the decrease in the size of transistors becomes a major performance bottleneck,” Gil added. “Our novel approach is to make the contact from the end of the carbon nanotube, which we show does not degrade device performance. This brings us a step closer to the goal of a carbon nanotube technology within the decade.”

Every once in a while, the size gets to me and a 1.8nm node is amazing. As for IBM’s 7nm chip, which was previewed this summer, there’s more about that in my July 15, 2015 posting.

Here’s a link to and a citation for the IBM paper,

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance by Qing Cao, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin†, Yu Zhu, Zhen Zhang‡, George S. Tulevski, Jianshi Tang, and Wilfried Haensch. Science 2 October 2015: Vol. 350 no. 6256 pp. 68-72 DOI: 10.1126/science.aac8006

This paper is behind a paywall.