Tag Archives: semiconductors

Cyborg bacteria to reduce carbon dioxide

This video is a bit technical but then it is about work being presented to chemists at the American Chemical Society’s (ACS) at the 254th National Meeting & Exposition Aug. 20 -24, 2017,

For a more plain language explanation, there’s an August 22, 2017 ACS news release (also on EurekAlert),

Photosynthesis provides energy for the vast majority of life on Earth. But chlorophyll, the green pigment that plants use to harvest sunlight, is relatively inefficient. To enable humans to capture more of the sun’s energy than natural photosynthesis can, scientists have taught bacteria to cover themselves in tiny, highly efficient solar panels to produce useful compounds.

“Rather than rely on inefficient chlorophyll to harvest sunlight, I’ve taught bacteria how to grow and cover their bodies with tiny semiconductor nanocrystals,” says Kelsey K. Sakimoto, Ph.D., who carried out the research in the lab of Peidong Yang, Ph.D. “These nanocrystals are much more efficient than chlorophyll and can be grown at a fraction of the cost of manufactured solar panels.”

Humans increasingly are looking to find alternatives to fossil fuels as sources of energy and feedstocks for chemical production. Many scientists have worked to create artificial photosynthetic systems to generate renewable energy and simple organic chemicals using sunlight. Progress has been made, but the systems are not efficient enough for commercial production of fuels and feedstocks.

Research in Yang’s lab at the University of California, Berkeley, where Sakimoto earned his Ph.D., focuses on harnessing inorganic semiconductors that can capture sunlight to organisms such as bacteria that can then use the energy to produce useful chemicals from carbon dioxide and water. “The thrust of research in my lab is to essentially ‘supercharge’ nonphotosynthetic bacteria by providing them energy in the form of electrons from inorganic semiconductors, like cadmium sulfide, that are efficient light absorbers,” Yang says. “We are now looking for more benign light absorbers than cadmium sulfide to provide bacteria with energy from light.”

Sakimoto worked with a naturally occurring, nonphotosynthetic bacterium, Moorella thermoacetica, which, as part of its normal respiration, produces acetic acid from carbon dioxide (CO2). Acetic acid is a versatile chemical that can be readily upgraded to a number of fuels, polymers, pharmaceuticals and commodity chemicals through complementary, genetically engineered bacteria.

When Sakimoto fed cadmium and the amino acid cysteine, which contains a sulfur atom, to the bacteria, they synthesized cadmium sulfide (CdS) nanoparticles, which function as solar panels on their surfaces. The hybrid organism, M. thermoacetica-CdS, produces acetic acid from CO2, water and light. “Once covered with these tiny solar panels, the bacteria can synthesize food, fuels and plastics, all using solar energy,” Sakimoto says. “These bacteria outperform natural photosynthesis.”

The bacteria operate at an efficiency of more than 80 percent, and the process is self-replicating and self-regenerating, making this a zero-waste technology. “Synthetic biology and the ability to expand the product scope of CO2 reduction will be crucial to poising this technology as a replacement, or one of many replacements, for the petrochemical industry,” Sakimoto says.

So, do the inorganic-biological hybrids have commercial potential? “I sure hope so!” he says. “Many current systems in artificial photosynthesis require solid electrodes, which is a huge cost. Our algal biofuels are much more attractive, as the whole CO2-to-chemical apparatus is self-contained and only requires a big vat out in the sun.” But he points out that the system still requires some tweaking to tune both the semiconductor and the bacteria. He also suggests that it is possible that the hybrid bacteria he created may have some naturally occurring analog. “A future direction, if this phenomenon exists in nature, would be to bioprospect for these organisms and put them to use,” he says.

For more insight into the work, check out Dexter Johnson’s Aug. 22, 2017 posting on his Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website),

“It’s actually a natural, overlooked feature of their biology,” explains Sakimoto in an e-mail interview with IEEE Spectrum. “This bacterium has a detoxification pathway, meaning if it encounters a toxic metal, like cadmium, it will try to precipitate it out, thereby detoxifying it. So when we introduce cadmium ions into the growth medium in which M. thermoacetica is hanging out, it will convert the amino acid cysteine into sulfide, which precipitates out cadmium as cadmium sulfide. The crystals then assemble and stick onto the bacterium through normal electrostatic interactions.”

I’ve just excerpted one bit, there’s more in Dexter’s posting.

IBM and a 5 nanometre chip

If this continues, they’re going to have change the scale from nano to pico. IBM has announced work on a 5 nanometre (5nm) chip in a June 5, 2017 news item on Nanotechnology Now,

IBM (NYSE: IBM), its Research Alliance partners GLOBALFOUNDRIES and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

A June 5, 2017 IBM news release, which originated the news item, spells out some of the details about IBM’s latest breakthrough,

The resulting increase in performance will help accelerate cognitive computing [emphasis mine], the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.”

The silicon nanosheet transistor demonstration, as detailed in the Research Alliance paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, and published by VLSI, proves that 5nm chips are possible, more powerful, and not too far off in the future.

Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

Building a New Switch

“This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in New York,” said Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”

IBM Research has explored nanosheet semiconductor technology for more than 10 years. This work is the first in the industry to demonstrate the feasibility to design and fabricate stacked nanosheet devices with electrical properties superior to FinFET architecture.

This same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node and its 20 billion transistors was applied to the nanosheet transistor architecture. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.

“Today’s announcement continues the public-private model collaboration with IBM that is energizing SUNY-Polytechnic’s, Albany’s, and New York State’s leadership and innovation in developing next generation technologies,” said Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute. “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities. SUNY Poly’s partnership with IBM and Empire State Development is a perfect example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society.”

Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), the proof of nanosheet architecture scaling to a 5nm node continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

I last wrote about IBM and computer chips in a July 15, 2015 posting regarding their 7nm chip. You may want to scroll down approximately 55% of the way where I note research from MIT (Massachusetts Institute of Technology) about metal nanoparticles with unexpected properties possibly having an impact on nanoelectronics.

Getting back to IBM, they have produced a slick video about their 5nm chip breakthrough,

Meanwhile, Katherine Bourzac provides technical detail in a June 5, 2017 posting on the Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website), Note: A link has been removed,

Researchers at IBM believe the future of the transistor is in stacked nanosheets. …

Today’s state-of-the-art transistor is the finFET, named for the fin-like ridges of current-carrying silicon that project from the chip’s surface. The silicon fins are surrounded on their three exposed sides by a structure called the gate. The gate switches the flow of current on, and prevents electrons from leaking out when the transistor is off. This design is expected to last from this year’s bleeding-edge process technology, the “10-nanometer” node, through the next node, 7 nanometers. But any smaller, and these transistors will become difficult to switch off: electrons will leak out, even with the three-sided gates.

So the semiconductor industry has been working on alternatives for the upcoming 5 nanometer node. One popular idea is to use lateral silicon nanowires that are completely surrounded by the gate, preventing electron leaks and saving power. This design is called “gate all around.” IBM’s new design is a variation on this. In their test chips, each transistor is made up of three stacked horizontal sheets of silicon, each only a few nanometers thick and completely surrounded by a gate.

Why a sheet instead of a wire? Huiming Bu, director of silicon integration and devices at IBM, says nanosheets can bring back one of the benefits of pre-finFET, planar designs. Designers used to be able to vary the width of a transistor to prioritize fast operations or energy efficiency. Varying the amount of silicon in a finFET transistor is not practicable because it would mean making some fins taller and other shorter. Fins must all be the same height due to manufacturing constraints, says Bu.

IBM’s nanosheets can range from 8 to 50 nanometers in width. “Wider gives you better performance but takes more power, smaller width relaxes performance but reduces power use,” says Bu. This will allow circuit designers to pick and choose what they need, whether they are making a power efficient mobile chip processor or designing a bank of SRAM memory. “We are bringing flexibility back to the designers,” he says.

The test chips have 30 billion transistors. …

It was a struggle trying to edit Bourzac’s posting with its good detail and clear writing. I encourage you to read it (June 5, 2017 posting) in its entirety.

As for where this drive downwards to the ‘ever smaller’ is going, there’s Dexter’s Johnson’s June 29, 2017 posting about another IBM team’s research on his Nanoclast blog on the IEEE website (Note: Links have been removed),

There have been increasing signs coming from the research community that carbon nanotubes are beginning to step up to the challenge of offering a real alternative to silicon-based complementary metal-oxide semiconductor (CMOS) transistors.

Now, researchers at IBM Thomas J. Watson Research Center have advanced carbon nanotube-based transistors another step toward meeting the demands of the International Technology Roadmap for Semiconductors (ITRS) for the next decade. The IBM researchers have fabricated a p-channel transistor based on carbon nanotubes that takes up less than half the space of leading silicon technologies while operating at a lower voltage.

In research described in the journal Science, the IBM scientists used a carbon nanotube p-channel to reduce the transistor footprint; their transistor contains all components to 40 square nanometers [emphasis mine], an ITRS roadmap benchmark for ten years out.

One of the keys to being able to reduce the transistor to such a small size is the use of the carbon nanotube as the channel in place of silicon. The nanotube is only 1 nanometer thick. Such thinness offers a significant advantage in electrostatics, so that it’s possible to reduce the device gate length to 10 nanometers without seeing the device performance adversely affected by short-channel effects. An additional benefit of the nanotubes is that the electrons travel much faster, which contributes to a higher level of device performance.

Happy reading!

A new type of diode from South Korea’s Ulsan National Institute of Science and Technology

A Feb. 8, 2017 news item on phys.org features a ‘dream’ diode from Ulsan National Institute of Science and Technology,

A team of researchers, affiliated with UNIST [Ulsan National Institute of Science and Technology] has created a new technique that greatly enhances the performance of Schottky Diodes (metal-semiconductor junction) used in electronic devices. Their research findings have attracted considerable attention within the scientific community by solving the contact resistance problem of metal-semiconductor, which had remained unsolved for almost 50 years.

As described in the January [2017] issue of Nano Letters, the researchers have created a new type of diode with a graphene insertion layer sandwiched between metal and semiconductor. This new technique blows all previous attemps out the water, as it is expected to significantly contribute to the semiconductor industry’s growth.

A Jan. 27, 2017 UNIST press release, (also on EurekAlert), which originated the news item, describes the research in greater detail,

The Schottky diode is one of the oldest and most representative semiconductor devices, formed by the junction of a semiconductor with a metal.  However, due to the atomic intermixing along the interface between two materials, it has been impossible to produce an ideal diode. (An ideal diode acts like a perfect conductor when voltage is applied forward biased and like a perfect insulator when voltage is applied reverse biased.)

graphene interlayer 2

The schematic view of internal photoemission (IPE) measurements on metal/n-Si(001) junctions with Ni, Pt, and Ti electrodes for with and without a graphene insertion layer.

Professor Kibog Park of Natural Science solved this problem by inserting a graphene layer at the metal-semiconductor interface. In the study, the research team demonstrated that this graphene layer, consisting of a single layer of carbon atoms can not only suppress the material intermixing substantially, but also matches well with the theoretical prediction.

“The sheets of graphene in graphite have a space between each sheet that shows a high electron density of quantum mechanics in that no atoms can pass through,” says Professor Park. “Therefore, with this single-layer graphene sandwiched between metal and semiconductor, it is possible to overcome the inevitable atomic diffusion problem.”

The study also has the physiological meaning of confirming the theoretical prediction that “In the case of silicon semiconductors, the electrical properties of the junction surfaces hardly change regardless of the type of metal they use,” according to Hoon Hahn Yoon (Combined M.S./Ph.D. student of Natural Science), the first author of the study.

The internal photoemission method was used to measure the electronic energy barrier of the newly-fabricated metal/graphene/n-Si(001) junction diodes. The Internal Photoemission (IPE) Measurement System in the image shown above has contributed greatly to these experiments. This system has been developed by four UNIST graduate students (Hoon Han Yoon, Sungchul Jung, Gahyun Choi, and Junhyung Kim), which was carried out as part of an undergraduate research project in 2012 and was supported by the Korea Foundation for the Advancement of Science and Creativity (KOFAC).

This is the internal photoemission (IPE) measurement system, developed by Hoon Hahn Yoon of Physics at UNIST.

Shown above is the Internal Photoemission (IPE) Measurement System, developed by Hoon Hahn Yoon, combined M.S./Ph.D. student of Natural Science at UNIST.

“Students have teamed up and carried out all the necessary steps for the research since they were undergraduates,” Professor Park says. “Therefore, this research is a perfect example of time, persistence, and patience paying off.”

This study has been jointly conducted by Professor Hu Young Jeong of the UNIST Central Research Facilities (UCRF), Professor Kwanpyo Kim of Natural Science, Professor Soon-Yong Kwon of Materials Science and Engineering, and Professor Yong Soo Kim of Ulsan University. It has been also supported by the National Research Foundation of Korea, Nuclear Research Basis Expansion Project, as well as the Global Ph.D Fellowship (GPF).

Here’s a link to and a citation for the paper,

Strong Fermi-Level Pinning at Metal/n-Si(001) Interface Ensured by Forming an Intact Schottky Contact with a Graphene Insertion Layer by Hoon Hahn Yoon, Sungchul Jung, Gahyun Choi, Junhyung Kim, Youngeun Jeon, Yong Soo Kim, Hu Young Jeong, Kwanpyo Kim, Soon-Yong Kwon, and Kibog Park. Nano Lett., 2017, 17 (1), pp 44–49 DOI: 10.1021/acs.nanolett.6b03137 Publication Date (Web): December 14, 2016

Copyright © 2016 American Chemical Society

This paper is behind a paywall.

Memory material with functions resembling synapses and neurons in the brain

This work comes from the University of Twente’s MESA+ Institute for Nanotechnology according to a July 8, 2016 news item on ScienceDaily,

Our brain does not work like a typical computer memory storing just ones and zeroes: thanks to a much larger variation in memory states, it can calculate faster consuming less energy. Scientists of the MESA+ Institute for Nanotechnology of the University of Twente (The Netherlands) now developed a ferro-electric material with a memory function resembling synapses and neurons in the brain, resulting in a multistate memory. …

A July 8, 2016 University of Twente press release, which originated the news item, provides more technical detail,

The material that could be the basic building block for ‘brain-inspired computing’ is lead-zirconium-titanate (PZT): a sandwich of materials with several attractive properties. One of them is that it is ferro-electric: you can switch it to a desired state, this state remains stable after the electric field is gone. This is called polarization: it leads to a fast memory function that is non-volatile. Combined with processor chips, a computer could be designed that starts much faster, for example. The UT scientists now added a thin layer of zinc oxide to the PZT, 25 nanometer thickness. They discovered that switching from one state to another not only happens from ‘zero’ to ‘one’ vice versa. It is possible to control smaller areas within the crystal: will they be polarized (‘flip’) or not?

In a PZT layer without zinc oxide (ZnO) there are basically two memorystates. Adding a nano layer of ZnO, every state in between is possible as well.

Multistate

By using variable writing times in those smaller areas, the result is that many states can be stored anywhere between zero and one. This resembles the way synapses and neurons ‘weigh’ signals in our brain. Multistate memories, coupled to transistors, could drastically improve the speed of pattern recognition, for example: our brain performs this kind of tasks consuming only a fraction of the energy a computer system needs. Looking at the graphs, the writing times seem quite long compared to nowaday’s processor speeds, but it is possible to create many memories in parallel. The function of the brain has already been mimicked in software like neurale networks, but in that case conventional digital hardware is still a limitation. The new material is a first step towards electronic hardware with a brain-like memory. Finding solutions for combining PZT with semiconductors, or even developing new kinds of semiconductors for this, is one of the next steps.

Here’s a link to and a citation for the paper,

Multistability in Bistable Ferroelectric Materials toward Adaptive Applications by Anirban Ghosh, Gertjan Koster, and Guus Rijnders. Advanced Functional Materials DOI: 10.1002/adfm.201601353 Version of Record online: 4 JUL 2016

© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

This paper is behind a paywall.

Diamond-based electronics?

A May 24, 2016 news item on ScienceDaily describes the latest research on using diamonds as semiconductors,

Along with being a “girl’s best friend,” diamonds also have remarkable properties that could make them ideal semiconductors. This is welcome news for electronics; semiconductors are needed to meet the rising demand for more efficient electronics that deliver and convert power.

The thirst for electronics is unlikely to cease and almost every appliance or device requires a suite of electronics that transfer, convert and control power. Now, researchers have taken an important step toward that technology with a new way to dope single crystals of diamonds, a crucial process for building electronic devices.

A May 24, 2016 American Institute of Physics (AIP) news release (also on EurekAlert), which originated the news item, provides more detail,

For power electronics, diamonds could serve as the perfect material. They are thermally conductive, which means diamond-based devices would dissipate heat quickly and easily, foregoing the need for bulky and expensive methods for cooling. Diamond can also handle high voltages and power. Electrical currents also flow through diamonds quickly, meaning the material would make for energy efficient devices.

But among the biggest challenges to making diamond-based devices is doping, a process in which other elements are integrated into the semiconductor to change its properties. Because of diamond’s rigid crystalline structure, doping is difficult.

Currently, you can dope diamond by coating the crystal with boron and heating it to 1450 degrees Celsius. But it’s difficult to remove the boron coating at the end. This method only works on diamonds consisting of multiple crystals stuck together. Because such polydiamonds have irregularities between the crystals, single-crystals would be superior semiconductors.

You can dope single crystals by injecting boron atoms while growing the crystals artificially. The problem is the process requires powerful microwaves that can degrade the quality of the crystal.

Now, Ma [Zhengqiang (Jack) Ma, an electrical and computer engineering professor at the University of Wisconsin-Madison] and his colleagues have found a way to dope single-crystal diamonds with boron at relatively low temperatures and without any degradation. The researchers discovered if you bond a single-crystal diamond with a piece of silicon doped with boron, and heat it to 800 degrees Celsius, which is low compared to the conventional techniques, the boron atoms will migrate from the silicon to the diamond. It turns out that the boron-doped silicon has defects such as vacancies, where an atom is missing in the lattice structure. Carbon atoms from the diamond will fill those vacancies, leaving empty spots for boron atoms.

This technique also allows for selective doping, which means more control when making devices. You can choose where to dope a single-crystal diamond simply by bonding the silicon to that spot.

The new method only works for P-type doping, where the semiconductor is doped with an element that provides positive charge carriers (in this case, the absence of electrons, called holes).

“We feel like we found a very easy, inexpensive, and effective way to do it,” Ma said. The researchers are already working on a simple device using P-type single-crystal diamond semiconductors.

But to make electronic devices like transistors, you need N-type doping that gives the semiconductor negative charge carriers (electrons). And other barriers remain. Diamond is expensive and single crystals are very small.

Still, Ma says, achieving P-type doping is an important step, and might inspire others to find solutions for the remaining challenges. Eventually, he said, single-crystal diamond could be useful everywhere — perfect, for instance, for delivering power through the grid.

Here’s an image the researchers have released,

Optical image of a diode array on a natural single crystalline diamond plate. (The image looks blurred due to light scattering by the array of small pads on top of the diamond plate.) Inset shows the deposited anode metal on top of heavy doped Si nanomembrane that is bonded to natural single crystalline diamond. CREDIT: Jung-Hun Seo

Optical image of a diode array on a natural single crystalline diamond plate. (The image looks blurred due to light scattering by the array of small pads on top of the diamond plate.) Inset shows the deposited anode metal on top of heavy doped Si nanomembrane that is bonded to natural single crystalline diamond. CREDIT: Jung-Hun Seo Courtesy: American Institute of Physics

Here’s a link to and a citation for the paper,

Thermal diffusion boron doping of single-crystal natural diamond by Jung-Hun Seo, Henry Wu, Solomon Mikael, Hongyi Mi, James P. Blanchard, Giri Venkataramanan, Weidong Zhou, Shaoqin Gong, Dane Morgan, and Zhenqiang Ma. J. Appl. Phys. 119, 205703 (2016); http://dx.doi.org/10.1063/1.4949327

This paper appears to be open access.

How vibrations affect nanoscale materials

A March 9, 2016 news item on ScienceDaily announces work concerning atomic vibrations,

All materials are made up of atoms, which vibrate. These vibrations, or ‘phonons’, are responsible, for example, for how electric charge and heat is transported in materials. Vibrations of metals, semiconductors, and insulators in are well studied; however, now materials are being nanosized to bring better performance to applications such as displays, sensors, batteries, and catalytic membranes. What happens to vibrations when a material is nanosized has until now not been understood.

A March 9, 2016 ETH Zurich press release (also on EurekAlert), which originated the news item, describes the world of vibration at the nanoscale and the potential impact this new information could have,

Soft Surfaces Vibrate Strongly

In a recent publication in Nature, ETH Professor Vanessa Wood and her colleagues explain what happens to atomic vibrations when materials are nanosized and how this knowledge can be used to systematically engineer nanomaterials for different applications.

The paper shows that when materials are made smaller than about 10 to 20 nanometers – that is, 5,000 times thinner than a human air – the vibrations of the outermost atomic layers on surface of the nanoparticle are large and play an important role in how this material behaves.

“For some applications, like catalysis, thermoelectrics, or superconductivity, these large vibrations may be good, but for other applications like LEDs or solar cells, these vibrations are undesirable,” explains Wood.

Indeed, the paper explains why nanoparticle-based solar cells have until now not met their full promise.  The researchers showed using both experiment and theory that surface vibrations interact with electrons to reduce the photocurrent in solar cells.

“Now that we have proven that surface vibrations are important, we can systematically design materials to suppress or enhance these vibrations,” say Wood.

Improving Solar Cells

Wood’s research group has worked for a long time on a particular type of nanomaterial – colloidal nanocrystals – semiconductors with a diameter of 2 to 10 nanometers.  These materials are interesting because their optical and electrical properties are dependent on their size, which can be easily changed during their synthesis.

These materials are now used commercially as red- and green-light emitters in LED-based TVs and are being explored as possible materials for low cost, solution-processed solar cells.  Researchers have noticed that placing certain atoms around the surface of the nanocrystal can improve the performance of solar cells. The reason why this worked had not been understood.  The work published in the Nature paper now gives the answer:  a hard shell of atoms can suppress the vibrations and their interaction with electrons.  This means a higher photocurrent and a higher efficiency solar cell.

Big Science to Study the Nanoscale

Experiments were conducted in Professor Wood’s labs at ETH Zurich and at the Swiss Spallation Neutron Source at the Paul Scherrer Institute. By observing how neutrons scatter off atoms in a material, it is possible to quantify how atoms in a material vibrate. To understand the neutron measurements, simulations of the atomic vibrations were run at the Swiss National Supercomputing Center (CSCS) in Lugano. Wood says, “without access to these large facilities, this work would not have been possible. We are incredibly fortunate here in Switzerland to have these world class facilities.”

The researchers have made available an image illustrating their work,

Vibrations of atoms in materials, the "phonons", are responsible for how electric charge and heat is transported in materials (Graphics: Deniz Bozyigit / ETH Zurich)

Vibrations of atoms in materials, the “phonons”, are responsible for how electric charge and heat is transported in materials (Graphics: Deniz Bozyigit / ETH Zurich)

Here’s a link to and a citation for the paper,

Soft surfaces of nanomaterials enable strong phonon interactions by Deniz Bozyigit, Nuri Yazdani, Maksym Yarema, Olesya Yarema, Weyde Matteo Mario Lin, Sebastian Volk, Kantawong Vuttivorakulchai, Mathieu Luisier, Fanni Juranyi, & Vanessa Wood. Nature (2016)  doi:10.1038/nature16977 Published online 09 March 2016

This paper is behind a paywall.

IBM, the Cognitive Era, and carbon nanotube electronics

IBM has a storied position in the field of nanotechnology due to the scanning tunneling microscope developed in the company’s laboratories. It was a Nobel Prize-winning breakthough which provided the impetus for nanotechnology applied research. Now, an Oct. 1, 2015 news item on Nanowerk trumpets another IBM breakthrough,

IBM Research today [Oct. 1, 2015] announced a major engineering breakthrough that could accelerate carbon nanotubes replacing silicon transistors to power future computing technologies.

IBM scientists demonstrated a new way to shrink transistor contacts without reducing performance of carbon nanotube devices, opening a pathway to dramatically faster, smaller and more powerful computer chips beyond the capabilities of traditional semiconductors.

While the Oct. 1, 2015 IBM news release, which originated the news item, does go on at length there’s not much technical detail (see the second to last paragraph in the excerpt for the little they do include) about the research breakthrough (Note: Links have been removed),

IBM’s breakthrough overcomes a major hurdle that silicon and any semiconductor transistor technologies face when scaling down. In any transistor, two things scale: the channel and its two contacts. As devices become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now. These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away. [emphasis mine]

Carbon nanotube chips could greatly improve the capabilities of high performance computers, enabling Big Data to be analyzed faster, increasing the power and battery life of mobile devices and the Internet of Things, and allowing cloud data centers to deliver services more efficiently and economically.

Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. With Moore’s Law running out of steam, shrinking the size of the transistor – including the channels and contacts – without compromising performance has been a vexing challenge troubling researchers for decades.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology. IBM’s new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip [emphasis mine], pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry. By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

“These chip innovations are necessary to meet the emerging demands of cloud computing, Internet of Things and Big Data systems,” said Dario Gil, vice president of Science & Technology at IBM Research. “As silicon technology nears its physical limits, new materials, devices and circuit architectures must be ready to deliver the advanced technologies that will be required by the Cognitive Computing era. This breakthrough shows that computer chips made of carbon nanotubes will be able to power systems of the future sooner than the industry expected.”

A New Contact for Carbon Nanotubes

Carbon nanotubes represent a new class of semiconductor materials that consist of single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device whose superior electrical properties promise several generations of technology scaling beyond the physical limits of silicon.

Electrons in carbon transistors can move more easily than in silicon-based devices, and the ultra-thin body of carbon nanotubes provide additional advantages at the atomic scale. Inside a chip, contacts are the valves that control the flow of electrons from metal into the channels of a semiconductor. As transistors shrink in size, electrical resistance increases within the contacts, which impedes performance. Until now, decreasing the size of the contacts on a device caused a commensurate drop in performance – a challenge facing both silicon and carbon nanotube transistor technologies.

IBM researchers had to forego traditional contact schemes and invented a metallurgical process akin to microscopic welding that chemically binds the metal atoms to the carbon atoms at the ends of nanotubes. This ‘end-bonded contact scheme’ allows the contacts to be shrunken down to below 10 nanometers without deteriorating performance of the carbon nanotube devices.

“For any advanced transistor technology, the increase in contact resistance due to the decrease in the size of transistors becomes a major performance bottleneck,” Gil added. “Our novel approach is to make the contact from the end of the carbon nanotube, which we show does not degrade device performance. This brings us a step closer to the goal of a carbon nanotube technology within the decade.”

Every once in a while, the size gets to me and a 1.8nm node is amazing. As for IBM’s 7nm chip, which was previewed this summer, there’s more about that in my July 15, 2015 posting.

Here’s a link to and a citation for the IBM paper,

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance by Qing Cao, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin†, Yu Zhu, Zhen Zhang‡, George S. Tulevski, Jianshi Tang, and Wilfried Haensch. Science 2 October 2015: Vol. 350 no. 6256 pp. 68-72 DOI: 10.1126/science.aac8006

This paper is behind a paywall.

TRIUMF accelerator used by US researchers to visualize properties of nanoscale materials

The US researchers are at the University of California at Los Angeles (UCLA) and while it’s not explicitly stated I’m assuming the accelerator they mention at TRIUMF (Canada’s national laboratory for particle and nuclear physics) has something special as there are accelerators in California and other parts of the US.

A July 15, 2015 news item on Nanotechnology Now announces the latest on visualizing the properties of nanoscale materials,

Scientists trying to improve the semiconductors that power our electronic devices have focused on a technology called spintronics as one especially promising area of research. Unlike conventional devices that use electrons’ charge to create power, spintronic devices use electrons’ spin. The technology is already used in computer hard drives and many other applications — and scientists believe it could eventually be used for quantum computers, a new generation of machines that use quantum mechanics to solve complex problems with extraordinary speed.

A July 15, 2015 UCLA news release, which originated the news item, expands on the theme and briefly mentions TRIUMF’s accelerator (Note: A link has been removed),

Emerging research has shown that one key to greatly improving performance in spintronics could be a class of materials called topological insulators. Unlike ordinary materials that are either insulators or conductors, topological insulators function as both simultaneously — on the inside, they are insulators but on their exteriors, they conduct electricity.

But topological insulators have certain defects that have so far limited their use in practical applications, and because they are so tiny, scientists have so far been unable to fully understand how the defects impact their functionality.

The UCLA researchers have overcome that challenge with a new method to visualize topological insulators at the nanoscale. An article highlighting the research, which was which led by Louis Bouchard, assistant professor of chemistry and biochemistry, and Dimitrios Koumoulis, a UCLA postdoctoral scholar, was published online in the Proceedings of the National Academy of Sciences.

The new method is the first use of beta‑detected nuclear magnetic resonance to study the effects of these defects on the properties of topological insulators.

The technique involves aiming a highly focused stream of ions at the topological insulator. To generate that beam of ions, the researchers used a large particle accelerator called a cyclotron, which accelerates protons through a spiral path inside the machine and forces them to collide with a target made of the chemical element tantalum. This collision produces lithium-8 atoms, which are ionized and slowed down to a desired energy level before they are implanted in the topological insulators.

In beta‑detected nuclear magnetic resonance, ions (in this case, the ionized lithium-8 atoms) of various energies are implanted in the material of interest (the topological insulator) to generate signals from the material’s layers of interest.

Bouchard said the method is particularly well suited for probing regions near the surfaces and interfaces of different materials.

In the UCLA research, the high sensitivity of the beta‑detected nuclear magnetic resonance technique and its ability to probe materials allowed the scientists to “see” the impacts of the defects in the topological insulators by viewing the electronic and magnetic properties beneath the surface of the material.

The researchers used the large TRIUMF cyclotron in Vancouver, British Columbia.

According to the UCLA news release, there were also researchers from the University of British Columbia, the University of Texas at Austin and Northwestern University *were* involved with the work.

Here’s a link to and a citation for the paper,

Nanoscale β-nuclear magnetic resonance depth imaging of topological insulators by Dimitrios Koumoulis, Gerald D. Morris, Liang He, Xufeng Kou, Danny King, Dong Wang, Masrur D. Hossain, Kang L. Wang, Gregory A. Fiete, Mercouri G. Kanatzidis, and Louis-S. Bouchard. PNAS July 14, 2015 vol. 112 no. 28 doi: 10.1073/pnas.1502330112

This paper is behind a paywall.

*’were’ added Jan. 20, 2016.

Replace silicon with black phosphorus instead of graphene?

I have two black phosphorus pieces. This first piece of research comes out of ‘La belle province’ or, as it’s more usually called, Québec (Canada).

Foundational research on phosphorene

There’s a lot of interest in replacing silicon for a number of reasons and, increasingly, there’s interest in finding an alternative to graphene.

A July 7, 2015 news item on Nanotechnology Now describes a new material for use as transistors,

As scientists continue to hunt for a material that will make it possible to pack more transistors on a chip, new research from McGill University and Université de Montréal adds to evidence that black phosphorus could emerge as a strong candidate.

In a study published today in Nature Communications, the researchers report that when electrons move in a phosphorus transistor, they do so only in two dimensions. The finding suggests that black phosphorus could help engineers surmount one of the big challenges for future electronics: designing energy-efficient transistors.

A July 7, 2015 McGill University news release on EurekAlert, which originated the news item, describes the field of 2D materials and the research into black phosphorus and its 2D version, phosperene (analogous to graphite and graphene),

“Transistors work more efficiently when they are thin, with electrons moving in only two dimensions,” says Thomas Szkopek, an associate professor in McGill’s Department of Electrical and Computer Engineering and senior author of the new study. “Nothing gets thinner than a single layer of atoms.”

In 2004, physicists at the University of Manchester in the U.K. first isolated and explored the remarkable properties of graphene — a one-atom-thick layer of carbon. Since then scientists have rushed to to investigate a range of other two-dimensional materials. One of those is black phosphorus, a form of phosphorus that is similar to graphite and can be separated easily into single atomic layers, known as phosphorene.

Phosphorene has sparked growing interest because it overcomes many of the challenges of using graphene in electronics. Unlike graphene, which acts like a metal, black phosphorus is a natural semiconductor: it can be readily switched on and off.

“To lower the operating voltage of transistors, and thereby reduce the heat they generate, we have to get closer and closer to designing the transistor at the atomic level,” Szkopek says. “The toolbox of the future for transistor designers will require a variety of atomic-layered materials: an ideal semiconductor, an ideal metal, and an ideal dielectric. All three components must be optimized for a well designed transistor. Black phosphorus fills the semiconducting-material role.”

The work resulted from a multidisciplinary collaboration among Szkopek’s nanoelectronics research group, the nanoscience lab of McGill Physics Prof. Guillaume Gervais, and the nanostructures research group of Prof. Richard Martel in Université de Montréal’s Department of Chemistry.

To examine how the electrons move in a phosphorus transistor, the researchers observed them under the influence of a magnetic field in experiments performed at the National High Magnetic Field Laboratory in Tallahassee, FL, the largest and highest-powered magnet laboratory in the world. This research “provides important insights into the fundamental physics that dictate the behavior of black phosphorus,” says Tim Murphy, DC Field Facility Director at the Florida facility.

“What’s surprising in these results is that the electrons are able to be pulled into a sheet of charge which is two-dimensional, even though they occupy a volume that is several atomic layers in thickness,” Szkopek says. That finding is significant because it could potentially facilitate manufacturing the material — though at this point “no one knows how to manufacture this material on a large scale.”

“There is a great emerging interest around the world in black phosphorus,” Szkopek says. “We are still a long way from seeing atomic layer transistors in a commercial product, but we have now moved one step closer.”

Here’s a link to and a citation for the paper,

Two-dimensional magnetotransport in a black phosphorus naked quantum well by V. Tayari, N. Hemsworth, I. Fakih, A. Favron, E. Gaufrès, G. Gervais, R. Martel & T. Szkopek. Nature Communications 6, Article number: 7702 doi:10.1038/ncomms8702 Published 07 July 2015

This is an open access paper.

The second piece of research into black phosphorus is courtesy of an international collaboration.

A phosporene transistor

A July 9, 2015 Technical University of Munich (TUM) press release (also on EurekAlert) describes the formation of a phosphorene transistor made possible by the introduction of arsenic,

Chemists at the Technische Universität München (TUM) have now developed a semiconducting material in which individual phosphorus atoms are replaced by arsenic. In a collaborative international effort, American colleagues have built the first field-effect transistors from the new material.

For many decades silicon has formed the basis of modern electronics. To date silicon technology could provide ever tinier transistors for smaller and smaller devices. But the size of silicon transistors is reaching its physical limit. Also, consumers would like to have flexible devices, devices that can be incorporated into clothing and the likes. However, silicon is hard and brittle. All this has triggered a race for new materials that might one day replace silicon.

Black arsenic phosphorus might be such a material. Like graphene, which consists of a single layer of carbon atoms, it forms extremely thin layers. The array of possible applications ranges from transistors and sensors to mechanically flexible semiconductor devices. Unlike graphene, whose electronic properties are similar to those of metals, black arsenic phosphorus behaves like a semiconductor.

The press release goes on to provide more detail about the collaboration and the research,

A cooperation between the Technical University of Munich and the University of Regensburg on the German side and the University of Southern California (USC) and Yale University in the United States has now, for the first time, produced a field effect transistor made of black arsenic phosphorus. The compounds were synthesized by Marianne Koepf at the laboratory of the research group for Synthesis and Characterization of Innovative Materials at the TUM. The field effect transistors were built and characterized by a group headed by Professor Zhou and Dr. Liu at the Department of Electrical Engineering at USC.

The new technology developed at TUM allows the synthesis of black arsenic phosphorus without high pressure. This requires less energy and is cheaper. The gap between valence and conduction bands can be precisely controlled by adjusting the arsenic concentration. “This allows us to produce materials with previously unattainable electronic and optical properties in an energy window that was hitherto inaccessible,” says Professor Tom Nilges, head of the research group for Synthesis and Characterization of Innovative Materials.

Detectors for infrared

With an arsenic concentration of 83 percent the material exhibits an extremely small band gap of only 0.15 electron volts, making it predestined for sensors which can detect long wavelength infrared radiation. LiDAR (Light Detection and Ranging) sensors operate in this wavelength range, for example. They are used, among other things, as distance sensors in automobiles. Another application is the measurement of dust particles and trace gases in environmental monitoring.

A further interesting aspect of these new, two-dimensional semiconductors is their anisotropic electronic and optical behavior. The material exhibits different characteristics along the x- and y-axes in the same plane. To produce graphene like films the material can be peeled off in ultra thin layers. The thinnest films obtained so far are only two atomic layers thick.

Here’s a link to and a citation for the paper,

Black Arsenic–Phosphorus: Layered Anisotropic Infrared Semiconductors with Highly Tunable Compositions and Properties by Bilu Liu, Marianne Köpf, Ahmad N. Abbas, Xiaomu Wang, Qiushi Guo, Yichen Jia, Fengnian Xia, Richard Weihrich, Frederik Bachhuber, Florian Pielnhofer, Han Wang, Rohan Dhall, Stephen B. Cronin, Mingyuan Ge1 Xin Fang, Tom Nilges, and Chongwu Zhou. DOI: 10.1002/adma.201501758 Article first published online: 25 JUN 2015

© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

This paper is behind a paywall.

Dexter Johnson, on his Nanoclast blog (on the Institute for Electrical and Electronics Engineers website), adds more information about black phosphorus and its electrical properties in his July 9, 2015 posting about the Germany/US collaboration (Note: Links have been removed),

Black phosphorus has been around for about 100 years, but recently it has been synthesized as a two-dimensional material—dubbed phosphorene in reference to its two-dimensional cousin, graphene. Black phosphorus is quite attractive for electronic applications like field-effect transistors because of its inherent band gap and it is one of the few 2-D materials to be a natively p-type semiconductor.

One final comment, I notice the Germany-US work was published weeks prior to the Canadian research suggesting that the TUM July 9, 2015 press release is an attempt to capitalize on the interest generated by the Canadian research. That’s a smart move.

Just how bendy are the new organic semiconductors?

In all the excitement about flexible electronics, an interesting question about performance, which seems to have been overlooked until now (how bendy are they?), is being answered by scientists, according to a May 5, 2015 University of Massachusetts at Amherst news release (also on EurekAlert),

A revolution is coming in flexible electronic technologies as cheaper, more flexible, organic transistors come on the scene to replace expensive, rigid, silicone-based semiconductors, but not enough is known about how bending in these new thin-film electronic devices will affect their performance, say materials scientists at the University of Massachusetts Amherst.

They are the first to apply inhomogeneous deformations, that is strain, to the conducting channel of an organic transistor and to understand the observed effects, says Reyes-Martinez [Marcos Reyes-Martinez], who conducted the series of experiments as part of his doctoral work.

As he explains, “This is relevant to today’s tech industry because transistors drive the logic of all the consumer electronics we use. In the screen on your smart phone, for example, every little pixel that makes up the image is turned on and off by hundreds of thousands or even millions of miniaturized transistors.”

“Traditionally, the transistors are rigid, made of an inorganic material such as silicon,” he adds. “We’re working with a crystalline semiconductorcalled rubrene, which is an organic, carbon-based material that has performance factors, such as charge-carrier mobility, surpassing those measured in amorphous silicon. Organic semiconductors are an interesting alternative to silicon because their properties can be tuned to make them easily processed, allowing them to coat a variety of surfaces, including soft substrates at relatively low temperatures. As a result, devices based on organic semiconductors are projected to be cheaper since they do not require high temperatures, clean rooms and expensive processing steps like silicon does.”

Until now, Reyes-Martinez notes, most researchers have focused on controlling the detrimental effects of mechanical deformation to atransistor’s electrical properties. But in their series of systematic experiments, the UMass Amherst team discovered that mechanical deformations only decrease performance under certain conditions, and actually can enhance or have no effect in other instances.

“Our goal was not only to show these effects, but to explain and understand them. What we’ve done istake advantage of the ordered structure of ultra-thin organic single crystals of rubrene to fabricate high-perfomance, thin-film transistors,” he says. “This is the first time that anyone has carried out detailed fundamental work at these length scales with a single crystal.”

Though single crystals were once thought to be too fragile for flexible applications, the UMass Amherst team found that crystals ranging in thickness from about 150 nanometers to 1 micrometer were thin enough to be wrinkled and applied to any elastomer substrate. Reyes-Martinez also notes, “Our experiments are especially important because they help scientists working on flexible electronic devices to determine performance limitations of new materials under extreme mechanical deformations, such as when electronic devices conform to skin.”

They developed an analytical model based on plate bending theoryto quantifythe different local strains imposed on the transistor structure by the wrinkle deformations. Using their model they are able to predict how different deformations modulate charge mobility, which no one had quantified before, Reyes-Martinez notes.

These contributions “represent a significant step forward in structure-function relationships in organic semiconductors, critical for the development of the next generation of flexible electronic devices,” the authors point out.

Here’s a link to and a citation for the paper,

Rubrene crystal field-effect mobility modulation via conducting channel wrinkling by Marcos A. Reyes-Martinez, Alfred J. Crosby,  & Alejandro L. Briseno. Nature Communications 6, Article number: 6948 doi:10.1038/ncomms7948 Published 05 May 2015

This is an open access paper.