Tag Archives: transistors

7nm (nanometre) chip shakeup

From time to time I check out the latest on attempts to shrink computer chips. In my July 11, 2014 posting I noted IBM’s announcement about developing a 7nm computer chip and later in my July 15, 2015 posting I noted IBM’s announcement of a working 7nm chip (from a July 9, 2015 IBM news release , “The breakthrough, accomplished in partnership with GLOBALFOUNDRIES and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE), could result in the ability to place more than 20 billion tiny switches — transistors — on the fingernail-sized chips that power everything from smartphones to spacecraft.”

I’m not sure what happened to the IBM/Global Foundries/Samsung partnership but Global Foundries recently announced that it will no longer be working on 7nm chips. From an August 27, 2018 Global Foundries news release,

GLOBALFOUNDRIES [GF] today announced an important step in its transformation, continuing the trajectory launched with the appointment of Tom Caulfield as CEO earlier this year. In line with the strategic direction Caulfield has articulated, GF is reshaping its technology portfolio to intensify its focus on delivering truly differentiated offerings for clients in high-growth markets.

GF is realigning its leading-edge FinFET roadmap to serve the next wave of clients that will adopt the technology in the coming years. The company will shift development resources to make its 14/12nm FinFET platform more relevant to these clients, delivering a range of innovative IP and features including RF, embedded memory, low power and more. To support this transition, GF is putting its 7nm FinFET program on hold indefinitely [emphasis mine] and restructuring its research and development teams to support its enhanced portfolio initiatives. This will require a workforce reduction, however a significant number of top technologists will be redeployed on 14/12nm FinFET derivatives and other differentiated offerings.

I tried to find a definition for FinFet but the reference to a MOSFET and in-gate transistors was too much incomprehensible information packed into a tight space, see the FinFET Wikipedia entry for more, if you dare.

Getting back to the 7nm chip issue, Samuel K. Moore (I don’t think he’s related to the Moore of Moore’s law) wrote an Aug. 28, 2018 posting on the Nanoclast blog (on the IEEE [Institute of Electronics and Electrical Engineers] website) which provides some insight (Note: Links have been removed),

In a major shift in strategy, GlobalFoundries is halting its development of next-generation chipmaking processes. It had planned to move to the so-called 7-nm node, then begin to use extreme-ultraviolet lithography (EUV) to make that process cheaper. From there, it planned to develop even more advanced lithography that would allow for 5- and 3-nanometer nodes. Despite having installed at least one EUV machine at its Fab 8 facility in Malta, N.Y., all those plans are now on indefinite hold, the company announced Monday.

The move leaves only three companies reaching for the highest rungs of the Moore’s Law ladder: Intel, Samsung, and TSMC.

It’s a huge turnabout for GlobalFoundries. …

GlobalFoundries rationale for the move is that there are not enough customers that need bleeding-edge 7-nm processes to make it profitable. “While the leading edge gets most of the headlines, fewer customers can afford the transition to 7 nm and finer geometries,” said Samuel Wang, research vice president at Gartner, in a GlobalFoundries press release.

“The vast majority of today’s fabless [emphasis mine] customers are looking to get more value out of each technology generation to leverage the substantial investments required to design into each technology node,” explained GlobalFoundries CEO Tom Caulfield in a press release. “Essentially, these nodes are transitioning to design platforms serving multiple waves of applications, giving each node greater longevity. This industry dynamic has resulted in fewer fabless clients designing into the outer limits of Moore’s Law. We are shifting our resources and focus by doubling down on our investments in differentiated technologies across our entire portfolio that are most relevant to our clients in growing market segments.”

(The dynamic Caulfield describes is something the U.S. Defense Advanced Research Agency is working to disrupt with its $1.5-billion Electronics Resurgence Initiative. Darpa’s [DARPA] partners are trying to collapse the cost of design and allow older process nodes to keep improving by using 3D technology.)

Fabless manufacturing is where the fabrication is outsourced and the manufacturing company of record is focused on other matters according to the Fabless manufacturing Wikipedia entry.

Roland Moore-Colyer (I don’t think he’s related to Moore of Moore’s law either) has written August 28, 2018 article for theinquirer.net which also explores this latest news from Global Foundries (Note: Links have been removed),

EVER PREPPED A SPREAD for a party to then have less than half the people you were expecting show up? That’s probably how GlobalFoundries [sic] feels at the moment.

The chip manufacturer, which was once part of AMD, had a fabrication process geared up for 7-nanometre chips which its customers – including AMD and Qualcomm – were expected to adopt.

But AMD has confirmed that it’s decided to move its 7nm GPU production to TSMC, and Intel is still stuck trying to make chips based on 10nm fabrication.

Arguably, this could mark a stymieing of innovation and cutting-edge designs for chips in the near future. But with processors like AMD’s Threadripper 2990WX overclocked to run at 6GHz across all its 32 cores, in the real-world PC fans have no need to worry about consumer chips running out of puff anytime soon. µ

That’s all folks.

Maybe that’s not all

Steve Blank in a Sept. 10, 2018 posting on the Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website) provides some provocative commentary on the Global Foundries announcement (Note: A link has been removed),

For most of our lives, the idea that computers and technology would get better, faster, and cheaper every year was as assured as the sun rising every morning. The story “GlobalFoundries Halts 7-nm Chip Development”  doesn’t sound like the end of that era, but for you and anyone who uses an electronic device, it most certainly is.

Technology innovation is going to take a different direction.

This story just goes on and on

There was a new development according to a Sept. 12, 2018 posting on the Nanoclast blog by, again, Samuel K. Moore (Note Links have been removed),

At an event today [sept. 12, 2018], Apple executives said that the new iPhone Xs and Xs Max will contain the first smartphone processor to be made using 7 nm manufacturing technology, the most advanced process node. Huawei made the same claim, to less fanfare, late last month and it’s unclear who really deserves the accolades. If anybody does, it’s TSMC, which manufactures both chips.

TSMC went into volume production with 7-nm tech in April, and rival Samsung is moving toward commercial 7-nm production later this year or in early 2019. GlobalFoundries recently abandoned its attempts to develop a 7 nm process, reasoning that the multibillion-dollar investment would never pay for itself. And Intel announced delays in its move to its next manufacturing technology, which it calls a 10-nm node but which may be equivalent to others’ 7-nm technology.

There’s a certain ‘soap opera’ quality to this with all the twists and turns.

3-D integration of nanotechnologies on a single computer chip

By integrating nanomaterials , a new technique for a 3D computer chip capable of handling today’s huge amount of data has been developed. Weirdly, the first two paragraphs of a July 5, 2017 news item on Nanowerk do not convey the main point (Note: A link has been removed),

As embedded intelligence is finding its way into ever more areas of our lives, fields ranging from autonomous driving to personalized medicine are generating huge amounts of data. But just as the flood of data is reaching massive proportions, the ability of computer chips to process it into useful information is stalling.

Now, researchers at Stanford University and MIT have built a new chip to overcome this hurdle. The results are published today in the journal Nature (“Three-dimensional integration of nanotechnologies for computing and data storage on a single chip”), by lead author Max Shulaker, an assistant professor of electrical engineering and computer science at MIT. Shulaker began the work as a PhD student alongside H.-S. Philip Wong and his advisor Subhasish Mitra, professors of electrical engineering and computer science at Stanford. The team also included professors Roger Howe and Krishna Saraswat, also from Stanford.

This image helps to convey the main points,

Instead of relying on silicon-based devices, a new chip uses carbon nanotubes and resistive random-access memory (RRAM) cells. The two are built vertically over one another, making a new, dense 3-D computer architecture with interleaving layers of logic and memory. Courtesy MIT

As I hove been quite impressed with their science writing, it was a bit surprising to find that the Massachusetts Institute of Technology (MIT) had issued this news release (news item) as it didn’t follow the ‘rules’, i.e., cover as many of the journalistic questions (Who, What, Where, When, Why, and, sometimes, How) as possible in the first sentence/paragraph. This is written more in the style of a magazine article and so the details take a while to emerge, from a July 5, 2017 MIT news release, which originated the news item,

Computers today comprise different chips cobbled together. There is a chip for computing and a separate chip for data storage, and the connections between the two are limited. As applications analyze increasingly massive volumes of data, the limited rate at which data can be moved between different chips is creating a critical communication “bottleneck.” And with limited real estate on the chip, there is not enough room to place them side-by-side, even as they have been miniaturized (a phenomenon known as Moore’s Law).

To make matters worse, the underlying devices, transistors made from silicon, are no longer improving at the historic rate that they have for decades.

The new prototype chip is a radical change from today’s chips. It uses multiple nanotechnologies, together with a new computer architecture, to reverse both of these trends.

Instead of relying on silicon-based devices, the chip uses carbon nanotubes, which are sheets of 2-D graphene formed into nanocylinders, and resistive random-access memory (RRAM) cells, a type of nonvolatile memory that operates by changing the resistance of a solid dielectric material. The researchers integrated over 1 million RRAM cells and 2 million carbon nanotube field-effect transistors, making the most complex nanoelectronic system ever made with emerging nanotechnologies.

The RRAM and carbon nanotubes are built vertically over one another, making a new, dense 3-D computer architecture with interleaving layers of logic and memory. By inserting ultradense wires between these layers, this 3-D architecture promises to address the communication bottleneck.

However, such an architecture is not possible with existing silicon-based technology, according to the paper’s lead author, Max Shulaker, who is a core member of MIT’s Microsystems Technology Laboratories. “Circuits today are 2-D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius,” says Shulaker. “If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits.”

The key in this work is that carbon nanotube circuits and RRAM memory can be fabricated at much lower temperatures, below 200 C. “This means they can be built up in layers without harming the circuits beneath,” Shulaker says.

This provides several simultaneous benefits for future computing systems. “The devices are better: Logic made from carbon nanotubes can be an order of magnitude more energy-efficient compared to today’s logic made from silicon, and similarly, RRAM can be denser, faster, and more energy-efficient compared to DRAM,” Wong says, referring to a conventional memory known as dynamic random-access memory.

“In addition to improved devices, 3-D integration can address another key consideration in systems: the interconnects within and between chips,” Saraswat adds.

“The new 3-D computer architecture provides dense and fine-grained integration of computating and data storage, drastically overcoming the bottleneck from moving data between chips,” Mitra says. “As a result, the chip is able to store massive amounts of data and perform on-chip processing to transform a data deluge into useful information.”

To demonstrate the potential of the technology, the researchers took advantage of the ability of carbon nanotubes to also act as sensors. On the top layer of the chip they placed over 1 million carbon nanotube-based sensors, which they used to detect and classify ambient gases.

Due to the layering of sensing, data storage, and computing, the chip was able to measure each of the sensors in parallel, and then write directly into its memory, generating huge bandwidth, Shulaker says.

Three-dimensional integration is the most promising approach to continue the technology scaling path set forth by Moore’s laws, allowing an increasing number of devices to be integrated per unit volume, according to Jan Rabaey, a professor of electrical engineering and computer science at the University of California at Berkeley, who was not involved in the research.

“It leads to a fundamentally different perspective on computing architectures, enabling an intimate interweaving of memory and logic,” Rabaey says. “These structures may be particularly suited for alternative learning-based computational paradigms such as brain-inspired systems and deep neural nets, and the approach presented by the authors is definitely a great first step in that direction.”

“One big advantage of our demonstration is that it is compatible with today’s silicon infrastructure, both in terms of fabrication and design,” says Howe.

“The fact that this strategy is both CMOS [complementary metal-oxide-semiconductor] compatible and viable for a variety of applications suggests that it is a significant step in the continued advancement of Moore’s Law,” says Ken Hansen, president and CEO of the Semiconductor Research Corporation, which supported the research. “To sustain the promise of Moore’s Law economics, innovative heterogeneous approaches are required as dimensional scaling is no longer sufficient. This pioneering work embodies that philosophy.”

The team is working to improve the underlying nanotechnologies, while exploring the new 3-D computer architecture. For Shulaker, the next step is working with Massachusetts-based semiconductor company Analog Devices to develop new versions of the system that take advantage of its ability to carry out sensing and data processing on the same chip.

So, for example, the devices could be used to detect signs of disease by sensing particular compounds in a patient’s breath, says Shulaker.

“The technology could not only improve traditional computing, but it also opens up a whole new range of applications that we can target,” he says. “My students are now investigating how we can produce chips that do more than just computing.”

“This demonstration of the 3-D integration of sensors, memory, and logic is an exceptionally innovative development that leverages current CMOS technology with the new capabilities of carbon nanotube field–effect transistors,” says Sam Fuller, CTO emeritus of Analog Devices, who was not involved in the research. “This has the potential to be the platform for many revolutionary applications in the future.”

This work was funded by the Defense Advanced Research Projects Agency [DARPA], the National Science Foundation, Semiconductor Research Corporation, STARnet SONIC, and member companies of the Stanford SystemX Alliance.

Here’s a link to and a citation for the paper,

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip by Max M. Shulaker, Gage Hills, Rebecca S. Park, Roger T. Howe, Krishna Saraswat, H.-S. Philip Wong, & Subhasish Mitra. Nature 547, 74–78 (06 July 2017) doi:10.1038/nature22994 Published online 05 July 2017

This paper is behind a paywall.

IBM and a 5 nanometre chip

If this continues, they’re going to have change the scale from nano to pico. IBM has announced work on a 5 nanometre (5nm) chip in a June 5, 2017 news item on Nanotechnology Now,

IBM (NYSE: IBM), its Research Alliance partners GLOBALFOUNDRIES and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

A June 5, 2017 IBM news release, which originated the news item, spells out some of the details about IBM’s latest breakthrough,

The resulting increase in performance will help accelerate cognitive computing [emphasis mine], the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.”

The silicon nanosheet transistor demonstration, as detailed in the Research Alliance paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, and published by VLSI, proves that 5nm chips are possible, more powerful, and not too far off in the future.

Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

Building a New Switch

“This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in New York,” said Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”

IBM Research has explored nanosheet semiconductor technology for more than 10 years. This work is the first in the industry to demonstrate the feasibility to design and fabricate stacked nanosheet devices with electrical properties superior to FinFET architecture.

This same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node and its 20 billion transistors was applied to the nanosheet transistor architecture. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.

“Today’s announcement continues the public-private model collaboration with IBM that is energizing SUNY-Polytechnic’s, Albany’s, and New York State’s leadership and innovation in developing next generation technologies,” said Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute. “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities. SUNY Poly’s partnership with IBM and Empire State Development is a perfect example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society.”

Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), the proof of nanosheet architecture scaling to a 5nm node continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

I last wrote about IBM and computer chips in a July 15, 2015 posting regarding their 7nm chip. You may want to scroll down approximately 55% of the way where I note research from MIT (Massachusetts Institute of Technology) about metal nanoparticles with unexpected properties possibly having an impact on nanoelectronics.

Getting back to IBM, they have produced a slick video about their 5nm chip breakthrough,

Meanwhile, Katherine Bourzac provides technical detail in a June 5, 2017 posting on the Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers] website), Note: A link has been removed,

Researchers at IBM believe the future of the transistor is in stacked nanosheets. …

Today’s state-of-the-art transistor is the finFET, named for the fin-like ridges of current-carrying silicon that project from the chip’s surface. The silicon fins are surrounded on their three exposed sides by a structure called the gate. The gate switches the flow of current on, and prevents electrons from leaking out when the transistor is off. This design is expected to last from this year’s bleeding-edge process technology, the “10-nanometer” node, through the next node, 7 nanometers. But any smaller, and these transistors will become difficult to switch off: electrons will leak out, even with the three-sided gates.

So the semiconductor industry has been working on alternatives for the upcoming 5 nanometer node. One popular idea is to use lateral silicon nanowires that are completely surrounded by the gate, preventing electron leaks and saving power. This design is called “gate all around.” IBM’s new design is a variation on this. In their test chips, each transistor is made up of three stacked horizontal sheets of silicon, each only a few nanometers thick and completely surrounded by a gate.

Why a sheet instead of a wire? Huiming Bu, director of silicon integration and devices at IBM, says nanosheets can bring back one of the benefits of pre-finFET, planar designs. Designers used to be able to vary the width of a transistor to prioritize fast operations or energy efficiency. Varying the amount of silicon in a finFET transistor is not practicable because it would mean making some fins taller and other shorter. Fins must all be the same height due to manufacturing constraints, says Bu.

IBM’s nanosheets can range from 8 to 50 nanometers in width. “Wider gives you better performance but takes more power, smaller width relaxes performance but reduces power use,” says Bu. This will allow circuit designers to pick and choose what they need, whether they are making a power efficient mobile chip processor or designing a bank of SRAM memory. “We are bringing flexibility back to the designers,” he says.

The test chips have 30 billion transistors. …

It was a struggle trying to edit Bourzac’s posting with its good detail and clear writing. I encourage you to read it (June 5, 2017 posting) in its entirety.

As for where this drive downwards to the ‘ever smaller’ is going, there’s Dexter’s Johnson’s June 29, 2017 posting about another IBM team’s research on his Nanoclast blog on the IEEE website (Note: Links have been removed),

There have been increasing signs coming from the research community that carbon nanotubes are beginning to step up to the challenge of offering a real alternative to silicon-based complementary metal-oxide semiconductor (CMOS) transistors.

Now, researchers at IBM Thomas J. Watson Research Center have advanced carbon nanotube-based transistors another step toward meeting the demands of the International Technology Roadmap for Semiconductors (ITRS) for the next decade. The IBM researchers have fabricated a p-channel transistor based on carbon nanotubes that takes up less than half the space of leading silicon technologies while operating at a lower voltage.

In research described in the journal Science, the IBM scientists used a carbon nanotube p-channel to reduce the transistor footprint; their transistor contains all components to 40 square nanometers [emphasis mine], an ITRS roadmap benchmark for ten years out.

One of the keys to being able to reduce the transistor to such a small size is the use of the carbon nanotube as the channel in place of silicon. The nanotube is only 1 nanometer thick. Such thinness offers a significant advantage in electrostatics, so that it’s possible to reduce the device gate length to 10 nanometers without seeing the device performance adversely affected by short-channel effects. An additional benefit of the nanotubes is that the electrons travel much faster, which contributes to a higher level of device performance.

Happy reading!

Switching of a single-atom channel

An Oct. 28, 2016 news item on phys.org announces a single-atom switch,

Robert Wolkow is no stranger to mastering the ultra-small and the ultra-fast. A pioneer in atomic-scale science with a Guinness World Record to boot (for a needle with a single atom at the point), Wolkow’s team, together with collaborators at the Max Plank Institute in Hamburg, have just released findings that detail how to create atomic switches for electricity, many times smaller than what is currently used.

What does it all mean? With applications for practical systems like silicon semi-conductor electronics, it means smaller, more efficient, more energy-conserving computers, as just one example of the technology revolution that is unfolding right before our very eyes (if you can squint that hard).

“This is the first time anyone’s seen a switching of a single-atom channel,” explains Wolkow, a physics professor at the University of Alberta and the Principal Research Officer at Canada’s National Institute for Nanotechnology. “You’ve heard of a transistor—a switch for electricity—well, our switches are almost a hundred times smaller than the smallest on the market today.”

An Oct. 28, 2016 University of Alberta news release by Jennifer Pascoe, which originated the news item, describes the research in more detail,

Today’s tiniest transistors operate at the 14 nanometer level, which still represents thousands of atoms. Wolkow’s and his team at the University of Alberta, NINT, and his spinoff QSi, have worked the technology down to just a few atoms. Since computers are simply a composition of many on/off switches, the findings point the way not only to ultra-efficient general purpose computing but also to a new path to quantum computing.

Green technology for the digital economy

“We’re using this technology to make ultra-green, energy-conserving general purpose computers but also to further the development of quantum computers. We are building the most energy conserving electronics ever, consuming about a thousand times less power than today’s electronics.”

While the new tech is small, the potential societal, economic, and environmental impact of Wolkow’s discovery is very large. Today, our electronics consume several percent of the world’s electricity.  As the size of the energy footprint of the digital economy increases, material and energy conservation is becoming increasingly important.

Wolkow says there are surprising benefits to being smaller, both for normal computers, and, for quantum computers too. “Quantum systems are characterized by their delicate hold on information. They’re ever so easily perturbed. Interestingly though, the smaller the system gets, the fewer upsets.” Therefore, Wolkow explains, you can create a system that is simultaneously amazingly small, using less material and churning through less energy, while holding onto information just right.

Smaller systems equal smaller environmental footprint

When the new technology is fully developed, it will lead to not only a smaller energy footprint but also more affordable systems for consumers. “It’s kind of amazing when everything comes together,” says Wolkow.

Wolkow is one of the few people in the world talking about atom-scale manufacturing and believes we are witnessing the beginning of the revolution to come. He and his team have been working with large-scale industry leader Lockheed Martin as the entry point to the market.

“It’s something you don’t even hear about yet, but atom-scale manufacturing is going to be world-changing. People think it’s not quite doable but, but we’re already making things out of atoms routinely. We aren’t doing it just because. We are doing it because the things we can make have ever more desirable properties. They’re not just smaller. They’re different and better. This is just the beginning of what will be at least a century of developments in atom-scale manufacturing, and it will be transformational.”

Bill Mah in a Nov. 1, 2016 article for the Edmonton Journal delves a little further into issues around making transistors smaller and the implications of a single-atom switch,

Current computers use transistors, which are essentially valves for flowing streams of electrons around a circuit. In recent years, engineers have found ways to make these devices smaller, but pushing electrons through narrow spaces raises the danger of the machines overheating and failing.

“The transistors get too hot so you have to run them slower and more gently, so we’re getting more power in modern computers because there are more transistors, but we can’t run them very quickly because they make a lot of heat and they actually just shut down and fail.”

The smallest transistors are currently about 14 nanometres. A nanometre is one-billionth of a metre and contains groupings of 1,000 or more atoms. The switches detailed by Wolkow and his colleagues will shrink them down to just a few atoms.

Potential benefits from the advance could lead to much more energy-efficient and smaller computers, an increasingly important consideration as the power consumption of digital devices keeps growing.

“The world is using about three per cent of our energy today on digital communications and computers,” Wolkow said. “Various reports I’ve seen say that it could easily go up to 10 or 15 per cent in a couple of decades, so it’s crucial that we get that under control.”

Wolkow’s team has received funding from companies such as Lockheed Martin and local investors.

The advances could also open a path to quantum computing. “It turns out these same building blocks … enable a quantum computer, so we’re kind of feverishly working on that at the same time.”

There is an animation illustrating a single-atom switch,

This animation represents an electrical current being switched on and off. Remarkably, the current is confined to a channel that is just one atom wide. Also, the switch is made of just one atom. When the atom in the centre feels an electric field tugging at it, it loses its electron. Once that electron is lost, the many electrons in the body of the silicon (to the left) have a clear passage to flow through. When the electric field is removed, an electron gets trapped in the central atom, switching the current off.  Courtesy: University of Alberta

Here’s a link to and a citation for the research paper,

Time-resolved single dopant charge dynamics in silicon by Mohammad Rashidi, Jacob A. J. Burgess, Marco Taucer, Roshan Achal, Jason L. Pitters, Sebastian Loth, & Robert A. Wolkow. Nature Communications 7, Article number: 13258 (2016)  doi:10.1038/ncomms13258 Published online: 26 October 2016

This paper is open access.

IBM, the Cognitive Era, and carbon nanotube electronics

IBM has a storied position in the field of nanotechnology due to the scanning tunneling microscope developed in the company’s laboratories. It was a Nobel Prize-winning breakthough which provided the impetus for nanotechnology applied research. Now, an Oct. 1, 2015 news item on Nanowerk trumpets another IBM breakthrough,

IBM Research today [Oct. 1, 2015] announced a major engineering breakthrough that could accelerate carbon nanotubes replacing silicon transistors to power future computing technologies.

IBM scientists demonstrated a new way to shrink transistor contacts without reducing performance of carbon nanotube devices, opening a pathway to dramatically faster, smaller and more powerful computer chips beyond the capabilities of traditional semiconductors.

While the Oct. 1, 2015 IBM news release, which originated the news item, does go on at length there’s not much technical detail (see the second to last paragraph in the excerpt for the little they do include) about the research breakthrough (Note: Links have been removed),

IBM’s breakthrough overcomes a major hurdle that silicon and any semiconductor transistor technologies face when scaling down. In any transistor, two things scale: the channel and its two contacts. As devices become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now. These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away. [emphasis mine]

Carbon nanotube chips could greatly improve the capabilities of high performance computers, enabling Big Data to be analyzed faster, increasing the power and battery life of mobile devices and the Internet of Things, and allowing cloud data centers to deliver services more efficiently and economically.

Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. With Moore’s Law running out of steam, shrinking the size of the transistor – including the channels and contacts – without compromising performance has been a vexing challenge troubling researchers for decades.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology. IBM’s new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip [emphasis mine], pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry. By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

“These chip innovations are necessary to meet the emerging demands of cloud computing, Internet of Things and Big Data systems,” said Dario Gil, vice president of Science & Technology at IBM Research. “As silicon technology nears its physical limits, new materials, devices and circuit architectures must be ready to deliver the advanced technologies that will be required by the Cognitive Computing era. This breakthrough shows that computer chips made of carbon nanotubes will be able to power systems of the future sooner than the industry expected.”

A New Contact for Carbon Nanotubes

Carbon nanotubes represent a new class of semiconductor materials that consist of single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device whose superior electrical properties promise several generations of technology scaling beyond the physical limits of silicon.

Electrons in carbon transistors can move more easily than in silicon-based devices, and the ultra-thin body of carbon nanotubes provide additional advantages at the atomic scale. Inside a chip, contacts are the valves that control the flow of electrons from metal into the channels of a semiconductor. As transistors shrink in size, electrical resistance increases within the contacts, which impedes performance. Until now, decreasing the size of the contacts on a device caused a commensurate drop in performance – a challenge facing both silicon and carbon nanotube transistor technologies.

IBM researchers had to forego traditional contact schemes and invented a metallurgical process akin to microscopic welding that chemically binds the metal atoms to the carbon atoms at the ends of nanotubes. This ‘end-bonded contact scheme’ allows the contacts to be shrunken down to below 10 nanometers without deteriorating performance of the carbon nanotube devices.

“For any advanced transistor technology, the increase in contact resistance due to the decrease in the size of transistors becomes a major performance bottleneck,” Gil added. “Our novel approach is to make the contact from the end of the carbon nanotube, which we show does not degrade device performance. This brings us a step closer to the goal of a carbon nanotube technology within the decade.”

Every once in a while, the size gets to me and a 1.8nm node is amazing. As for IBM’s 7nm chip, which was previewed this summer, there’s more about that in my July 15, 2015 posting.

Here’s a link to and a citation for the IBM paper,

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance by Qing Cao, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin†, Yu Zhu, Zhen Zhang‡, George S. Tulevski, Jianshi Tang, and Wilfried Haensch. Science 2 October 2015: Vol. 350 no. 6256 pp. 68-72 DOI: 10.1126/science.aac8006

This paper is behind a paywall.

Two Irelands-US research initiative: UNITE

Happy St. Patrick’s Day on March 17, 2015! Researchers, building on an earlier collaborative effort (FOCUS), have announced a new US-Ireland initiative, from a March 9, 2015 news item on Nanowerk,

A three-year US-Ireland collaborative scientific project aims to reduce power consumption and increase battery life in mobile devices. Researchers will explore new semiconducting materials in the miniaturisation of transistors which are essential to all portable devices.

Leading researchers from the Republic of Ireland (Tyndall National Institute & Dublin City University), Northern Ireland (Queens University Belfast) and the US (University of Texas at Dallas) – each funded by their respective government agencies – are collaborating to develop ultra-efficient electronic materials through the UNITE project: Understanding the Nature of Interfaces in Two-Dimensional Electronic Devices.

A March 9, 2015 (?) Tyndall National Institute press release, which originated the news item, details the project, the researchers, and the hoped for applications,

UNITE will create and test the properties of atomically-thin, 2-dimensional layers of semiconductors called, Transition Metal Dichalcogenides or TMD’s for short. These layers are 100,000 times smaller than the smallest thing the human eye can see. The properties these materials have displayed to date suggest that they could facilitate extremely efficient power usage and high performance computing.

Tyndall’s lead researcher Dr. Paul Hurley explains that, “materials that we are currently reliant on, such as silicon, are soon expected to reach the limit of their performance. If we want to continue to increase performance, while maintaining or even reducing power consumption, it is important to explore these new TMD materials.”

The application of these materials in transistors could prolong the battery charge life of portable devices and phones, as well as having applications in larger more power intensive operations like data storage and server centres. This will have obvious environmental benefits through the reduction of electrical energy consumed by information and communication technologies as well as benefitting consumers.

UNITE builds on a previous highly successful US-Ireland collaborative project between these academic research partners called FOCUS. The success of this project played a role in demonstrating why funders should back the new project, including training for five graduate students in the USA and Ireland, as well as student exchanges between the Institutes, which will provide a broader scientific and cultural experience for the graduates involved.

The press release goes on to describe FOCUS, the researchers’ prior collaborative project,

UNITE builds on a previous highly successful US-Ireland collaborative project between these academic research partners called FOCUS. The success of this project played a role in demonstrating why funders should back the new project, including training for five graduate students in the USA and Ireland, as well as student exchanges between the Institutes, which will provide a broader scientific and cultural experience for the graduates involved.

A March 13, 2015 (?) Tyndall National Institute press release describes both an event to celebrate the success enjoyed by FOCUS and gives specifics about the achievements,

FOCUS, a US-Ireland collaborative project will be presented as a research success highlight to An Taoiseach Enda Kenny on St. Patrick’s Day along with industry and academic leaders, at a Science Foundation Ireland (SFI) event in Washington DC. The event is to celebrate the SFI St. Patrick’s Day Science Medal Award and is an important occasion on the St. Patrick’s Day schedule in the USA.

Funded under the US-Ireland R&D Partnership Programme, FOCUS (Future Oxides and Channel Materials for Ultimate Scaling) linked researchers in Tyndall National Institute (Dr Paul Hurley), Dublin City University (Prof. Greg Hughes), Queen’s University Belfast (Dr David McNeill) and the University of Texas at Dallas (Prof. Robert Wallace).

Billions of silicon-based transistors are crammed onto a single chip and used in billions of electronic devices around the world such as computers, laptops and mobile phones. The FOCUS project group investigated if it was possible to use alternative materials to silicon in the active channels of transistors to improve their energy efficiency and battery life.

The consortium explored using Germanium and Indium-Gallium-Arsenide in combination with high dielectric constant oxides as a viable alternative to silicon. Their research was able to improve the electronic properties of these alternative semiconductor/oxide interfaces to the level needed for practical device applications and the outcomes of their research have now moved to industry for practical application.

The key achievements from the project include:

  • Strong collaboration with Intel USA and Intel Ireland resulting in Paul Hurley receiving the Intel Outstanding Researcher Award in 2012
  • Presentation of the project findings at the annual Intel European Research and Innovation Conference
  • 3 Postdocs trained and 5 PhDs awarded in areas of strong interest to semiconductor manufacturers
  • 35 journal papers published
  • 2011 article on InGaAs surface treatment optimisation listed as one of the top 10 most cited articles in the Journal of Applied Physics in 2012
  • 10 invited presentations at key scientific conferences
  • University research partnership established between Tyndall National Institute and University of Texas at Dallas
  • Project highlighted in Irish press, The Times of India and The Irish Voice
  • Visit by the Consul General of Ireland to University of Texas at Dallas
  • Numerous students and staff exchanges between all partner institutions

Good luck to the UNITE project!

Public domain biotechnology: biological transistors from Stanford University

Andrew Myers’ Mar. 28, 2013 article for the Stanford School of Medicine’s magazine (Inside Stanford Medicine) profiles some research which stands as a bridge between electronics and biology and could lead to biological computing,

… now a team of Stanford University bioengineers has taken computing beyond mechanics and electronics into the living realm of biology. In a paper published March 28 in Science, the team details a biological transistor made from genetic material — DNA and RNA — in place of gears or electrons. The team calls its biological transistor the “transcriptor.”

“Transcriptors are the key component behind amplifying genetic logic — akin to the transistor and electronics,” said Jerome Bonnet, PhD, a postdoctoral scholar in bioengineering and the paper’s lead author.

Here’s a description of the transcriptor (biological transistor) and biological computers (from the article),

In electronics, a transistor controls the flow of electrons along a circuit. Similarly, in biologics, a transcriptor controls the flow of a specific protein, RNA polymerase, as it travels along a strand of DNA.

“We have repurposed a group of natural proteins, called integrases, to realize digital control over the flow of RNA polymerase along DNA, which in turn allowed us to engineer amplifying genetic logic,” said Endy [Drew Endy, PhD, assistant professor of bioengineering and the paper’s senior author].

Using transcriptors, the team has created what are known in electrical engineering as logic gates that can derive true-false answers to virtually any biochemical question that might be posed within a cell.

They refer to their transcriptor-based logic gates as “Boolean Integrase Logic,” or “BIL gates” for short.

Transcriptor-based gates alone do not constitute a computer, but they are the third and final component of a biological computer that could operate within individual living cells.

The article also offers a description of Boolean logic and the workings of standard computers,

Digital logic is often referred to as “Boolean logic,” after George Boole, the mathematician who proposed the system in 1854. Today, Boolean logic typically takes the form of 1s and 0s within a computer. Answer true, gate open; answer false, gate closed. Open. Closed. On. Off. 1. 0. It’s that basic. But it turns out that with just these simple tools and ways of thinking you can accomplish quite a lot.

“AND” and “OR” are just two of the most basic Boolean logic gates. An “AND” gate, for instance, is “true” when both of its inputs are true — when “a” and “b” are true. An “OR” gate, on the other hand, is true when either or both of its inputs are true.

In a biological setting, the possibilities for logic are as limitless as in electronics, Bonnet explained. “You could test whether a given cell had been exposed to any number of external stimuli — the presence of glucose and caffeine, for instance. BIL gates would allow you to make that determination and to store that information so you could easily identify those which had been exposed and which had not,” he said.

Here’s how they created a transcriptor (from the article),

To create transcriptors and logic gates, the team used carefully calibrated combinations of enzymes — the integrases mentioned earlier — that control the flow of RNA polymerase along strands of DNA. If this were electronics, DNA is the wire and RNA polymerase is the electron.

“The choice of enzymes is important,” Bonnet said. “We have been careful to select enzymes that function in bacteria, fungi, plants and animals, so that bio-computers can be engineered within a variety of organisms.”

On the technical side, the transcriptor achieves a key similarity between the biological transistor and its semiconducting cousin: signal amplification.

Refreshingly the team made this decision (from the article),

To bring the age of the biological computer to a much speedier reality, Endy and his team have contributed all of BIL gates to the public domain so that others can immediately harness and improve upon the tools.

“Most of biotechnology has not yet been imagined, let alone made true. By freely sharing important basic tools everyone can work better together,” Bonnet said.

Here’s a citation and a link to the researchers’ paper in Science,

Amplifying Genetic Logic Gates by Jerome Bonnet, Peter Yin, Monica E. Ortiz, Pakpoom Subsoontorn, and Drew Endy. Science 1232758 Published online 28 March 2013 [DOI:10.1126/science.1232758]

This paper is behind a paywall. As for Myers’ article, it’s well worth reading for its clear explanations and forays into computing history.

Shake hands with Sacha, a robot controlled by carbon nanotube transistors

Since we use computer chips built from silicon in any number devices including robots, the announcement of a robot controlled by the first computer chip built entirely of a material other silicon bears notice. From the Mar. 15, 2013 news item on Nanowerk (Note: Links have been removed),

A group of Stanford researchers recently debuted the first robot controlled by a computer chip built entirely from carbon nanotube transistors, which many scientists predict may eventually replace silicon.

While scientists have produced simple demonstrations of working carbon nanotube circuit components in the past, the Stanford team, led by Professor of Electrical Engineering Philip Wong and Associate Professor of Electrical Engineering and Computer Science Subhasish Mitra Ph.D. ’00, was able to demonstrate an actual subsystem composed entirely of the material.

The news item was originated by a Mar. 7, 2013 article by Nikhita Obeegadoo for the Stanford Daily, where she noted,

The project was presented in the form of a robot named Sacha at the 2013 International Solid-State Circuits Conference (“Sacha, the Stanford Carbon Nanotube Controlled Handshaking Robot”), which was held in San Francisco. According to Mitra, the robot was created to demonstrate the development of a system that can function despite the errors caused by inherently imperfect nanotubes, which have posed issues for research teams working with carbon nanotubes in the past.

“Through several generations of technology, devices keep getting smaller and denser, and silicon will no longer be the best material for the purpose in about ten years,” Guha [Supratik Guha, director of physical sciences at IBM’s Yorktown Heights Research Center] said. “For needs that are close to atomic dimensions, carbon nanotubes have just the right shape and the right electrical behavior.”

Eric Juma on his eponymous blog offers more insight into the project in his Mar. 16, 2013 posting,

… The robot contained a carbon nanotube capacitor, a device found in many touchscreens, connected to another nanotube circuit, which turned the analog signal from the capacitor into a digital signal, which was transmitted to the microprocessor that contained CNT transistors. The microporcessor then sent a signal to a motor on the hand of the robot, which shook the person’s hand that touched the capacitors embedded in it.

This is not the first example of carbon nanotube circuitry, but it is the first example of CNTs being produced at mass for a microprocessor and circuit that were integrated. This advancement showed that it is possible to produce mass amounts of CNTs and have them integrate succesfully into a complex system. Although the size of the CNTs in this system are far from the optimal size of 10nm, it is a good starting point, and the nanotubes still can be much further refined.

Carbon nanotubes, although perfect in theory for microprocessors, present new challenges for engineers. The greatest challenge is the actual integration of CNTs into circuitry. Nanotubes often force themselves into a tangled position, which can cause circuits to fail without warning.

Juma gives a good explanation for why there is so much interest in carbon nanotubes in the field of electronics and he provides links to more information about it all. (There’s a video about carbon nanotubes and their various shapes and structures in my Mar. 15, 2013 posting about them.)

Sacha will be seen (or perhaps the work will simply be presented by Max Shulaker?) next in Switzerland at a Mar. 25, 2013 workshop (FED ’13; Functionality-Enhanced Devices Workshop) at the EPFl (École Polytechnique Fédérale de Lausanne.

Cells and transistors

Analog/digital, is there a difference? After reading the latest from MIT’s (Massachusetts Institute of Technology) Research Laboratory Electronics (RLE), the answer turns out to be no, when it comes to transistors. From the Sept. 29, 2011 news item on Nanowerk,

A transistor is basically a switch: When it’s on, it conducts electricity; when it’s off, it doesn’t. [emphases mine] In a computer chip, those two states represent 0s and 1s.

But in moving between its nonconductive and conductive states, a transistor passes through every state in between — slightly conductive, moderately conductive, fairly conductive — just as a car accelerating from zero to 60 passes through every speed in between. Because the transistors in a computer chip are intended to perform binary logic operations, they’re designed to make those transitional states undetectable. [emphases mine]

The MIT researchers will be discussing their work using analog transistors to increase the concentrations of two different proteins in cells. From the news item on Nanowerk,

At the Biomedical Circuits and Systems Conference in San Diego in November, Sarpeshkar [Rahul Sarpeshkar, associate professor of electrical engineering], research scientist Lorenzo Turicchia, postdoc Ramiz Daniel and graduate student Sung Sik Woo, all of RLE, will present a paper in which they use analog electronic circuits to model two different types of interactions between proteins and DNA in the cell. The circuits mimic the behaviors of the cell with remarkable accuracy, but perhaps more important, they do it with far fewer transistors than a digital model would require.

Here’s a graphic representation of transistors in a cell (downloaded from the MIT News Office page for this research,

Graphic: Christine Daniloff

This works seems to be signaling (pun noted) a change in how systems biology and synthetic biology researchers think about biological systems. From the Sept. 28, 2011 news item by Larry Hardesty for the MIT News Office,

Since the completion of the Human Genome Project, two thriving new disciplines — synthetic biology and systems biology — have emerged from the observation that in some ways, the sequences of chemical reactions that lead to protein production in cells are a lot like electronic circuits. In general, researchers in both fields tend to analyze reactions in terms of binary oppositions: If a chemical is present, one thing happens; if the chemical is absent, a different thing happens.

But Rahul Sarpeshkar, an associate professor of electrical engineering in MIT’s Research Laboratory of Electronics (RLE), thinks that’s the wrong approach. “The signals in cells are not ones or zeroes,” Sarpeshkar says. “That’s an overly simplified abstraction that is kind of a first, crude, useful approximation for what cells do. But everybody knows that’s really wrong.”

From what I understand of the synthetic biology and systems biology communities, this is a major change.