Tag Archives: Vera Abramova

Better RRAM memory devices in the short term

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Given my recent spate of posts about computing and the future of the chip (list to follow at the end of this post), this Rice University [Texas, US] research suggests that some improvements to current memory devices might be coming to the market in the near future. From a July 12, 2014 news item on Azonano,

Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

A July 10, 2014 Rice University news release, which originated the news item, provides more detail,

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Here’s a link to and a citation for the paper,

Nanoporous Silicon Oxide Memory by Gunuk Wang, Yang Yang, Jae-Hwang Lee, Vera Abramova, Huilong Fei, Gedeng Ruan, Edwin L. Thomas, and James M. Tour. Nano Lett., Article ASAP DOI: 10.1021/nl501803s Publication Date (Web): July 3, 2014

Copyright © 2014 American Chemical Society

This paper is behind a paywall.

As for my recent spate of posts on computers and chips, there’s a July 11, 2014 posting about IBM, a 7nm chip, and much more; a July 9, 2014 posting about Intel and its 14nm low-power chip processing and plans for a 10nm chip; and, finally, a June 26, 2014 posting about HP Labs and its plans for memristive-based computing and their project dubbed ‘The Machine’.

Like water for graphene nanoribbons

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Reference to magical realism and fiction aside (Like Water for Chocolate by Laura Esquivel), it turns out that water is integral to the formation of very long, very thin graphene nanoribbons. A July 30, 2011 Rice University news release describes the phenomenon, a two year research odyssey, and the scientific ‘accident’ which led researchers to the discovery,

New research at Rice University shows how water makes it practical to form long graphene nanoribbons less than 10 nanometers wide.

And it’s unlikely that many of the other labs currently trying to harness the potential of graphene, a single-atom sheet of carbon, for microelectronics would have come up with the technique the Rice researchers found while they were looking for something else.

The discovery by lead author Vera Abramova and co-author Alexander Slesarev, both graduate students in the lab of Rice chemist James Tour, appears online this month in the American Chemical Society journal ACS Nano.

A bit of water adsorbed from the atmosphere was found to act as a mask in a process that begins with the creation of patterns via lithography and ends with very long, very thin graphene nanoribbons. The ribbons form wherever water gathers at the wedge between the raised pattern and the graphene surface.

The water formation is called a meniscus; it is created when the surface tension of a liquid causes it to curve [in a convex or concave manner]. In the Rice process, the meniscus mask protects a tiny ribbon of graphene from being etched away when the pattern is removed.

Tour said any method to form long wires only a few nanometers wide should catch the interest of microelectronics manufacturers as they approach the limits of their ability to miniaturize circuitry. “They can never take advantage of the smallest nanoscale devices if they can’t address them with a nanoscale wire,” he said. “Right now, manufacturers can make small features, or make big features and put them where they want them. But to have both has been difficult. To be able to pattern a line this thin right where you want it is a big deal because it permits you to take advantage of the smallness in size of nanoscale devices.”

Tour said water’s tendency to adhere to surfaces is often annoying, but in this case it’s essential to the process. “There are big machines that are used in electronics research that are often heated to hundreds of degrees under ultrahigh vacuum to drive off all the water that adheres to the inside surfaces,” he said. “Otherwise there’s always going to be a layer of water. In our experiments, water accumulates at the edge of the structure and protects the graphene from the reactive ion etching (RIE). So in our case, that residual water is the key to success.

…

Abramova and Slesarev had set out to fabricate nanoribbons by inverting a method developed by another Rice lab to make narrow gaps in materials. The original method utilized the ability of some metals to form a native oxide layer that expands and shields material just on the edge of the metal mask. The new method worked, but not as expected.

“We first suspected there was some kind of shadowing,” Abramova said. But other metals that didn’t expand as much, if at all, showed no difference, nor did varying the depth of the pattern. “I was basically looking for anything that would change something.”

It took two years to develop and test the meniscus theory, during which the researchers also confirmed its potential to create sub-10-nanometer wires from other kinds of materials, including platinum. They also constructed field-effect transistors to check the electronic properties of graphene nanoribbons.

To be sure that water does indeed account for the ribbons, they tried eliminating its effect by first drying the patterns by heating them under vacuum, and then by displacing the water with acetone to eliminate the meniscus. In both cases, no graphene nanoribbons were created.

The researchers are working to better control the nanoribbons’ width, and they hope to refine the nanoribbons’ edges, which help dictate their electronic properties.

“With this study, we figured out you don’t need expensive tools to get these narrow features,” Tour said. “You can use the standard tools [;] a fab line already has to make features that are smaller than 10 nanometers.”

Here’s a link to and a citation for the research paper,

Meniscus-Mask Lithography for Narrow Graphene Nanoribbons by Vera Abramova, Alexander S. Slesarev, and James M. Tour. ACS Nano, Article ASAP DOI: 10.1021/nn403057t Publication Date (Web): July 23, 2013
Copyright © 2013 American Chemical Society

This paper is behind a paywall.

Dexter Johnson in his July30, 2013 posting on the Nanoclast blog (on the IEEE [Institute of Electrical and Electronics Engineers]) notes that this use of water is counter-intuitive,

In [an] ironic twist, the water that most lithography processes try avoid and eliminate at great cost is the same water that makes this new lithography process work.