Tag Archives: flash memory

Nucleic acid-based memory storage

We’re running out of memory. To be more specific, there are two problems: the supply of silicon and a limit to how much silicon-based memory can store. An April 27, 2016 news item on Nanowerk announces a nucleic acid-based approach to solving the memory problem,

A group of Boise State [Boise State University in Idaho, US] researchers, led by associate professor of materials science and engineering and associate dean of the College of Innovation and Design Will Hughes, is working toward a better way to store digital information using nucleic acid memory (NAM).

An April 25, 2016 Boise State University news release, which originated the news item, expands on the theme of computer memory and provides more details about the approach,

It’s no secret that as a society we generate vast amounts of data each year. So much so that the 30 billion watts of electricity used annually by server farms today is roughly equivalent to the output of 30 nuclear power plants.

And the demand keeps growing. The global flash memory market is predicted to reach $30.2 billion this year, potentially growing to $80.3 billion by 2025. Experts estimate that by 2040, the demand for global memory will exceed the projected supply of silicon (the raw material used to store flash memory). Furthermore, electronic memory is rapidly approaching its fundamental size limits because of the difficulty in storing electrons in small dimensions.

Hughes, with post-doctoral researcher Reza Zadegan and colleagues Victor Zhirnov (Semiconductor Research Corporation), Gurtej Sandhun (Micron Technology Inc.) and George Church (Harvard University), is looking to DNA molecules to solve the problem. Nucleic acid — the “NA” in “DNA” — far surpasses electronic memory in retention time, according to the researchers, while also providing greater information density and energy of operation.

Their conclusions are outlined in an invited commentary in the prestigious journal Nature Materials published earlier this month.

“DNA is the data storage material of life in general,” said Hughes. “Because of its physical and chemical properties, it also may become the data storage material of our lives.” It may sound like science fiction, but Hughes will participate in an invitation-only workshop this month at the Intelligence Advanced Research Projects Activity (IARPA) Agency to envision a portable DNA hard drive that would have 500 Terabytes of searchable data – that’s about the the size of the Library of Congress Web Archive.

“When information bits are encoded into polymer strings, researchers and manufacturers can manage and manipulate physical, chemical and biological information with standard molecular biology techniques,” the paper [in Nature Materials?] states.

Cost-competitive technologies to read and write DNA could lead to real-world applications ranging from artificial chromosomes, digital hard drives and information-management systems, to a platform for watermarking and tracking genetic content or next-generation encryption tools that necessitate physical rather than electronic embodiment.

Here’s how it works. Current binary code uses 0’s and 1’s to represent bits of information. A computer program then accesses a specific decoder to turn the numbers back into usable data. With nucleic acid memory, 0’s and 1’s are replaced with the nucleotides A, T, C and G. Known as monomers, they are covalently bonded to form longer polymer chains, also known as information strings.

Because of DNA’s superior ability to store data, DNA can contain all the information in the world in a small box measuring 10 x 10 x 10 centimeters cubed. NAM could thus be used as a sustainable time capsule for massive, scientific, financial, governmental, historical, genealogical, personal and genetic records.

Better yet, DNA can store digital information for a very long time – thousands to millions of years. Currently, usable information has been extracted from DNA in bones that are 700,000 years old, making nucleic acid memory a promising archival material. And nucleic acid memory uses 100 million times less energy than storing data electronically in flash, and the data can live on for generations.

At Boise State, Hughes and Zadegan are examining DNA’s stability under extreme conditions. DNA strands are subjected to temperatures varying from negative 20 degrees Celsius to 100 degrees Celsius, and to a variety of UV exposures to see if they can still retain their information. What they’re finding is that much less information is lost with NAM than with the current state of the industry.

Here’s a link to and a citation for the Nature Materials paper,

Nucleic acid memory by Victor Zhirnov, Reza M. Zadegan, Gurtej S. Sandhu, George M. Church, & William L. Hughes. Nature Materials 15, 366–370 (2016)  doi:10.1038/nmat4594 Published online 23 March 2016

This paper is behind a paywall.

Korean researchers fabricate cross-shaped memristors

I’ve been a bit late getting this Korean research concerning memristors into a posting. A Jan. 30, 2016 news item on Nanotechnology Now announces a new means of fabricating memristors,

Along with the fast development of modern information technology, charge-based memories, such as DRAM and flash memory, are being aggressively scaled down to meet the current trend of small size devices. A memory device with high density, faster speed, and low power consumption is desired to satisfy Moore’s law in the next few decades. Among the candidates of next-generation memory devices, cross-bar-shaped non-volatile resistive memory (memristor) is one of the most attractive solutions for its non-volatility, faster access speed, ultra-high density and easier fabrication process.

Conventional memristors are usually fabricated through conventional optical, imprint, and e-beam lithographic approaches. However, to meet Moore’s law, the assembly of memristors comprised of 1-dimensional (1D) nanowires must be demonstrated to achieve cell dimensions beyond limit of state-of-art lithographic techniques, thus allowing one to fully exploit the scaling potential of high density memory array.

Prof. Tae-Woo Lee (Dept. of Materials Science and Engineering) and his research team have developed a rapid printing technology for high density and scalable memristor array composed of cross-bar-shaped metal nanowires. The research team, which consists of Prof. Tae-Woo Lee, research professor Wentao Xu, and doctoral student Yeongjun Lee at POSTECH [Pohang University of Science and Technology], Korea, published their findings in Advanced Materials.

A Jan. 28, 2016 POSTECH news release, which originated the news item, expands on the theme,

They applied an emerging technique, electrohydrohynamic nanowire printing (e-NW printing), which directly prints highly-aligned nanowire array on a large scale into the fabrication of microminiature memristors, with cross-bar-shaped conductive Cu nanowires jointed with a nanometer-scale CuxO layer. The metal-oxide-metal structure resistive memory device exhibited excellent electrical performance with reproducible resistive switching behavior.

This simple and fast fabrication process avoids conventional vacuum techniques to significantly reduce the industrial-production cost and time. This method paved the way to the future down-scaling of electronic circuits, since 1D conductors represent a logical way to extreme scaling of data processing devices in the single-digit nanometer scale.

They also succeeded in printing memristor array with various shapes, such as parallel lines with adjustable pitch, grids, and waves which can offer a future stretchable memory for integration into textile to serve as a basic building block for smart fabrics and wearable electronics.

“This technology reduces lead time and cost remarkably compared with existing manufacturing methods of cross-bar-shaped nanowire memory and simplifies its method of construction,” said Prof. Lee. “In particular, this technology will be used as a source technology to realize smart fabric, wearable computers, and textile electronic devices.”

Here’s a link to and a citation for the paper,

[Nanowires:] Simple, Inexpensive, and Rapid Approach to Fabricate Cross-Shaped Memristors Using an Inorganic-Nanowire-Digital-Alignment Technique and a One-Step Reduction Process by Wentao Xu, Yeongjun Lee, Sung-Yong Min, Cheolmin Park, andTae-Woo Lee. Advanced Materials Volume 28, Issue 3 January 20, 2016 Page 591  DOI: 10.1002/adma.201503153 Article first published online: 20 NOV 2015

© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

This paper is behind a paywall.

Memristor shakeup

New discoveries suggest that memristors do not function as was previously theorized. (For anyone who wants a memristor description, there’s this Wikipedia entry.) From an Oct. 13, 2015 posting by Alexander Hellemans for the Nanoclast blog (on the IEEE [Institute for Electrical and Electronics Engineers]), Note: Links have been removed,

What’s going to replace flash? The R&D arms of several companies including Hewlett Packard, Intel, and Samsung think the answer might be memristors (also called resistive RAM, ReRAM, or RRAM). These devices have a chance at unseating the non-volatile memory champion because, they use little energy, are very fast, and retain data without requiring power. However, new research indicates that they don’t work in quite the way we thought they do.

The fundamental mechanism at the heart of how a memristor works is something called an “imperfect point contact,” which was predicted in 1971, long before anybody had built working devices. When voltage is applied to a memristor cell, it reduces the resistance across the device. This change in resistance can be read out by applying another, smaller voltage. By inverting the voltage, the resistance of the device is returned to its initial value, that is, the stored information is erased.

Over the last decade researchers have produced two commercially promising types of memristors: electrochemical metallization memory (ECM) cells, and valence change mechanism memory (VCM) cells.

Now international research teams lead by Ilia Valov at the Peter Grünberg Institute in Jülich, Germany, report in Nature Nanotechnology and Advanced Materials that they have identified new processes that erase many of the differences between EMC and VCM cells.

Valov and coworkers in Germany, Japan, Korea, Greece, and the United States started investigating memristors that had a tantalum oxide electrolyte and an active tantalum electrode. “Our studies show that these two types of switching mechanisms in fact can be bridged, and we don’t have a purely oxygen type of switching as was believed, but that also positive [metal] ions, originating from the active electrode, are mobile,” explains Valov.

Here are links to and citations for both papers,

Graphene-Modified Interface Controls Transition from VCM to ECM Switching Modes in Ta/TaOx Based Memristive Devices by Michael Lübben, Panagiotis Karakolis, Vassilios Ioannou-Sougleridis, Pascal Normand, Pangiotis Dimitrakis, & Ilia Valov. Advanced Materials DOI: 10.1002/adma.201502574 First published: 10 September 2015

Nanoscale cation motion in TaOx, HfOx and TiOx memristive systems by Anja Wedig, Michael Luebben, Deok-Yong Cho, Marco Moors, Katharina Skaja, Vikas Rana, Tsuyoshi Hasegawa, Kiran K. Adepalli, Bilge Yildiz, Rainer Waser, & Ilia Valov. Nature Nanotechnology (2015) doi:10.1038/nnano.2015.221 Published online 28 September 2015

Both papers are behind paywalls.

Better RRAM memory devices in the short term

Given my recent spate of posts about computing and the future of the chip (list to follow at the end of this post), this Rice University [Texas, US] research suggests that some improvements to current memory devices might be coming to the market in the near future. From a July 12, 2014 news item on Azonano,

Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

A July 10, 2014 Rice University news release, which originated the news item, provides more detail,

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Here’s a link to and a citation for the paper,

Nanoporous Silicon Oxide Memory by Gunuk Wang, Yang Yang, Jae-Hwang Lee, Vera Abramova, Huilong Fei, Gedeng Ruan, Edwin L. Thomas, and James M. Tour. Nano Lett., Article ASAP DOI: 10.1021/nl501803s Publication Date (Web): July 3, 2014

Copyright © 2014 American Chemical Society

This paper is behind a paywall.

As for my recent spate of posts on computers and chips, there’s a July 11, 2014 posting about IBM, a 7nm chip, and much more; a July 9, 2014 posting about Intel and its 14nm low-power chip processing and plans for a 10nm chip; and, finally, a June 26, 2014 posting about HP Labs and its plans for memristive-based computing and their project dubbed ‘The Machine’.

Resistive memory from University of California Riverside (replacing flash memory in mobile devices) and Boise State University (neuron chips)

Today, (Aug. 19, 2 013)I have two items on memristors. First, Dexter Johnson provides some context for understanding why a University of California Riverside research team’s approach to creating memristors is exciting some interest in his Aug. 17, 2013 posting (Nanoclast blog on the IEEE [Institute of Electrical and Electronics Engineers] website), Note: Links have been removed,

The heralding of the memristor, or resistive memory, and the long-anticipated demise of flash memory have both been tracking on opposite trajectories with resistive memory expected to displace flash ever since the memristor was first discovered by Stanley Williams’ group at Hewlett Packard in 2008.

The memristor has been on a rapid development track ever since and has been promised to be commercially available as early as 2014, enabling 10 times greater embedded memory for mobile devices than currently available.

The obsolescence of flash memory at the hands of the latest nanotechnology has been predicted for longer than the commercial introduction of the memristor. But just at the moment it appears it’s going to reach its limits in storage capacity along comes a new way to push its capabilities to new heights, sometimes thanks to a nanomaterial like graphene.

In addition to the graphene promise, Dexter goes on to discuss another development,  which could push memory capabilities and which is mentioned in an Aug. 14, 2013 news item on ScienceDaily (and elsewhere),

A team at the University of California, Riverside Bourns College of Engineering has developed a novel way to build what many see as the next generation memory storage devices for portable electronic devices including smart phones, tablets, laptops and digital cameras.

The device is based on the principles of resistive memory [memristor], which can be used to create memory cells that are smaller, operate at a higher speed and offer more storage capacity than flash memory cells, the current industry standard. Terabytes, not gigbytes, will be the norm with resistive memory.

The key advancement in the UC Riverside research is the creation of a zinc oxide nano-island on silicon. It eliminates the need for a second element called a selector device, which is often a diode.

The Aug. 13, 2013 University of California Riverside news release by Sean Nealon, which originated the news item, further describes the limitations of flash memory and reinforces the importance of being able to eliminate a component (selector device),

Flash memory has been the standard in the electronics industry for decades. But, as flash continues to get smaller and users want higher storage capacity, it appears to reaching the end of its lifespan, Liu [Jianlin Liu, a professor of electrical engineering] said.

With that in mind, resistive memory is receiving significant attention from academia and the electronics industry because it has a simple structure, high-density integration, fast operation and long endurance.

Researchers have also found that resistive memory can be scaled down in the sub 10-nanometer scale. (A nanometer is one-billionth of a meter.) Current flash memory devices are roughly using a feature size twice as large.

Resistive memory usually has a metal-oxide-metal structure in connection with a selector device. The UC Riverside team has demonstrated a novel alternative way by forming self-assembled zinc oxide nano-islands on silicon. Using a conductive atomic force microscope, the researchers observed three operation modes from the same device structure, essentially eliminating the need for a separate selector device.

Here’s a link to and a citation for the researchers’ published paper,

Multimode Resistive Switching in Single ZnO Nanoisland System by Jing Qi, Mario Olmedo, Jian-Guo Zheng, & Jianlin Liu. Scientific Reports 3, Article number: 2405 doi:10.1038/srep02405 Published 12 August 2013

This study is open access.

Meanwhile, Boise State University (Idaho, US) is celebrating a new project, CIF: Small: Realizing Chip-scale Bio-inspired Spiking Neural Networks with Monolithically Integrated Nano-scale Memristors, which was announced in an Aug. 17, 2013 news item on Azonano,

Electrical and computer engineering faculty Elisa Barney Smith, Kris Campbell and Vishal Saxena are joining forces on a project titled “CIF: Small: Realizing Chip-scale Bio-inspired Spiking Neural Networks with Monolithically Integrated Nano-scale Memristors.”

Team members are experts in machine learning (artificial intelligence), integrated circuit design and memristor devices. Funded by a three-year, $500,000 National Science Foundation grant, they have taken on the challenge of developing a new kind of computing architecture that works more like a brain than a traditional digital computer.

“By mimicking the brain’s billions of interconnections and pattern recognition capabilities, we may ultimately introduce a new paradigm in speed and power, and potentially enable systems that include the ability to learn, adapt and respond to their environment,” said Barney Smith, who is the principal investigator on the grant.

The Aug. 14, 2013 Boise State University news release by Kathleen Tuck, which originated the news item, describes the team’s focus on mimicking the brain’s capabilities ,

One of the first memristors was built in Campbell’s Boise State lab, which has the distinction of being one of only five or six labs worldwide that are up to the task.

The team’s research builds on recent work from scientists who have derived mathematical algorithms to explain the electrical interaction between brain synapses and neurons.

“By employing these models in combination with a new device technology that exhibits similar electrical response to the neural synapses, we will design entirely new computing chips that mimic how the brain processes information,” said Barney Smith.

Even better, these new chips will consume power at an order of magnitude lower than current computing processors, despite the fact that they match existing chips in physical dimensions. This will open the door for ultra low-power electronics intended for applications with scarce energy resources, such as in space, environmental sensors or biomedical implants.

Once the team has successfully built an artificial neural network, they will look to engage neurobiologists in parallel to what they are doing now. A proposal for that could be written in the coming year.

Barney Smith said they hope to send the first of the new neuron chips out for fabrication within weeks.

With the possibility that HP Labs will make its ‘memristor chips‘ commercially available in 2014 and neuron chips fabricated for the Boise State University researchers within weeks of this Aug. 19, 2013 date, it seems that memristors have been developed at a lightning fast pace. It’s been a fascinating process to observe.

Memristors and transparent electronics in Oregon

The Sept. 14, 2012 news release from Oregon State University (OSU) features some very careful wording around the concept of a memristor.  First, here’s the big picture news,

The transparent electronics that were pioneered at Oregon State University may find one of their newest applications as a next-generation replacement for some uses of non-volatile flash memory, a multi-billion dollar technology nearing its limit of small size and information storage capacity.

Researchers at OSU have confirmed that zinc tin oxide, an inexpensive and environmentally benign compound, has significant potential for use in this field, and could provide a new, transparent technology where computer memory is based on resistance, instead of an electron charge.

Here’s where it starts to get interesting,

This resistive random access memory, or RRAM, is referred to by some researchers as a “memristor.”  [emphasis mine] Products using this approach could become even smaller, faster and cheaper than the silicon transistors that have revolutionized modern electronics – and transparent as well.

Transparent electronics offer potential for innovative products that don’t yet exist, like information displayed on an automobile windshield, or surfing the web on the glass top of a coffee table.

“Flash memory has taken us a long way with its very small size and low price,” said John Conley, a professor in the OSU School of Electrical Engineering and Computer Science. “But it’s nearing the end of its potential, and memristors are a leading candidate to continue performance improvements.”

Memristors have a simple structure, are able to program and erase information rapidly, and consume little power. They accomplish a function similar to transistor-based flash memory, but with a different approach. Whereas traditional flash memory stores information with an electrical charge, RRAM accomplishes this with electrical resistance. Like flash, it can store information as long as it’s needed.

Flash memory computer chips are ubiquitous in almost all modern electronic products, ranging from cell phones and computers to video games and flat panel televisions.

I like how they note that some scientists call these devices memristors thereby sidestepping at least some of the controversy as to what exactly constitute a memristor (my latest piece which mentions a critique of the memristor concept was posted Sept. 6, 2012).

The news release gets a little confusing here,

Some of the best opportunities for these new amorphous oxide semiconductors are not so much for memory chips, but with thin-film, flat panel displays, researchers say. [emphasis mine] Private industry has already shown considerable interest in using them for the thin-film transistors that control liquid crystal displays, and one compound approaching commercialization is indium gallium zinc oxide.

But indium and gallium are getting increasingly expensive, and zinc tin oxide – also a transparent compound – appears to offer good performance with lower cost materials. The new research also shows that zinc tin oxide can be used not only for thin-film transistors, but also for memristive memory, Conley said, an important factor in its commercial application.

More work is needed to understand the basic physics and electrical properties of the new compounds, researchers said.

There was no mention of amorphous oxide semiconductors until the portion I’ve highlighted . If I’ve understood what follows correctly, there’s a new class of semiconductor for use in thin film applications (transparent electronics): an amorphous oxide semiconductor and the most promising material for commercial purposes is indium gallium zinc oxide. The other oxide mentioned in the excerpt, zinc tin oxide, can be used both for thin film applications and memristive applications.

This memristor story has certainly moved some interesting directions as it continues to develop.