Tag Archives: Samsung Electronics

TrueNorth, a brain-inspired chip architecture from IBM and Cornell University

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As a Canadian, “true north” is invariably followed by “strong and free” while singing our national anthem. For many Canadians it is almost the only phrase that is remembered without hesitation.  Consequently, some of the buzz surrounding the publication of a paper celebrating ‘TrueNorth’, a brain-inspired chip, is a bit disconcerting. Nonetheless, here is the latest IBM (in collaboration with Cornell University) news from an Aug. 8, 2014 news item on Nanowerk,

Scientists from IBM unveiled the first neurosynaptic computer chip to achieve an unprecedented scale of one million programmable neurons, 256 million programmable synapses and 46 billion synaptic operations per second per watt. At 5.4 billion transistors, this fully functional and production-scale chip is currently one of the largest CMOS chips ever built, yet, while running at biological real time, it consumes a minuscule 70mW—orders of magnitude less power than a modern microprocessor. A neurosynaptic supercomputer the size of a postage stamp that runs on the energy equivalent of a hearing-aid battery, this technology could transform science, technology, business, government, and society by enabling vision, audition, and multi-sensory applications.

An Aug. 7, 2014 IBM news release, which originated the news item, provides an overview of the multi-year process this breakthrough represents (Note: Links have been removed),

There is a huge disparity between the human brain’s cognitive capability and ultra-low power consumption when compared to today’s computers. To bridge the divide, IBM scientists created something that didn’t previously exist—an entirely new neuroscience-inspired scalable and efficient computer architecture that breaks path with the prevailing von Neumann architecture used almost universally since 1946.

This second generation chip is the culmination of almost a decade of research and development, including the initial single core hardware prototype in 2011 and software ecosystem with a new programming language and chip simulator in 2013.

The new cognitive chip architecture has an on-chip two-dimensional mesh network of 4096 digital, distributed neurosynaptic cores, where each core module integrates memory, computation, and communication, and operates in an event-driven, parallel, and fault-tolerant fashion. To enable system scaling beyond single-chip boundaries, adjacent chips, when tiled, can seamlessly connect to each other—building a foundation for future neurosynaptic supercomputers. To demonstrate scalability, IBM also revealed a 16-chip system with sixteen million programmable neurons and four billion programmable synapses.

“IBM has broken new ground in the field of brain-inspired computers, in terms of a radically new architecture, unprecedented scale, unparalleled power/area/speed efficiency, boundless scalability, and innovative design techniques. We foresee new generations of information technology systems – that complement today’s von Neumann machines – powered by an evolving ecosystem of systems, software, and services,” said Dr. Dharmendra S. Modha, IBM Fellow and IBM Chief Scientist, Brain-Inspired Computing, IBM Research. “These brain-inspired chips could transform mobility, via sensory and intelligent applications that can fit in the palm of your hand but without the need for Wi-Fi. This achievement underscores IBM’s leadership role at pivotal transformational moments in the history of computing via long-term investment in organic innovation.”

The Defense Advanced Research Projects Agency (DARPA) has funded the project since 2008 with approximately $53M via Phase 0, Phase 1, Phase 2, and Phase 3 of the Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) program. Current collaborators include Cornell Tech and iniLabs, Ltd.

Building the Chip

The chip was fabricated using Samsung’s 28nm process technology that has a dense on-chip memory and low-leakage transistors.

“It is an astonishing achievement to leverage a process traditionally used for commercially available, low-power mobile devices to deliver a chip that emulates the human brain by processing extreme amounts of sensory information with very little power,” said Shawn Han, vice president of Foundry Marketing, Samsung Electronics. “This is a huge architectural breakthrough that is essential as the industry moves toward the next-generation cloud and big-data processing. It’s a pleasure to be part of technical progress for next-generation through Samsung’s 28nm technology.”

The event-driven circuit elements of the chip used the asynchronous design methodology developed at Cornell Tech [aka Cornell University] and refined with IBM since 2008.

“After years of collaboration with IBM, we are now a step closer to building a computer similar to our brain,” said Professor Rajit Manohar, Cornell Tech.

The combination of cutting-edge process technology, hybrid asynchronous-synchronous design methodology, and new architecture has led to a power density of 20mW/cm2 which is nearly four orders of magnitude less than today’s microprocessors.

Advancing the SyNAPSE Ecosystem

The new chip is a component of a complete end-to-end vertically integrated ecosystem spanning a chip simulator, neuroscience data, supercomputing, neuron specification, programming paradigm, algorithms and applications, and prototype design models. The ecosystem supports all aspects of the programming cycle from design through development, debugging, and deployment.

To bring forth this fundamentally different technological capability to society, IBM has designed a novel teaching curriculum for universities, customers, partners, and IBM employees.

Applications and Vision

This ecosystem signals a shift in moving computation closer to the data, taking in vastly varied kinds of sensory data, analyzing and integrating real-time information in a context-dependent way, and dealing with the ambiguity found in complex, real-world environments.

Looking to the future, IBM is working on integrating multi-sensory neurosynaptic processing into mobile devices constrained by power, volume and speed; integrating novel event-driven sensors with the chip; real-time multimedia cloud services accelerated by neurosynaptic systems; and neurosynaptic supercomputers by tiling multiple chips on a board, creating systems that would eventually scale to one hundred trillion synapses and beyond.

Building on previously demonstrated neurosynaptic cores with on-chip, online learning, IBM envisions building learning systems that adapt in real world settings. While today’s hardware is fabricated using a modern CMOS process, the underlying architecture is poised to exploit advances in future memory, 3D integration, logic, and sensor technologies to deliver even lower power, denser package, and faster speed.

I have two articles that may prove of interest, Peter Stratton’s Aug. 7, 2014 article for The Conversation provides an easy-to-read introduction to both brains, human and computer, (as they apply to this research) and TrueNorth (h/t phys.org also hosts Stratton’s article). There’s also an Aug. 7, 2014 article by Rob Farber for techenablement.com which includes information from a range of text and video sources about TrueNorth and cognitive computing as it’s also known (well worth checking out).

Here’s a link to and a citation for the paper,

A million spiking-neuron integrated circuit with a scalable communication network and interface by Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernard Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra S. Modha. Science 8 August 2014: Vol. 345 no. 6197 pp. 668-673 DOI: 10.1126/science.1254642

This paper is behind a paywall.

Extending memristive theory

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This is kind of fascinating. A German research team based at JARA (Jülich Aachen Research Alliance) is suggesting that memristive theory be extended beyond passive components in their paper about Resistive Memory Cells (ReRAM) which was recently published in Nature Communications. From the Apr. 26, 2013 news item on Azonano,

Resistive memory cells (ReRAM) are regarded as a promising solution for future generations of computer memories. They will dramatically reduce the energy consumption of modern IT systems while significantly increasing their performance.

Unlike the building blocks of conventional hard disk drives and memories, these novel memory cells are not purely passive components but must be regarded as tiny batteries. This has been demonstrated by researchers of Jülich Aachen Research Alliance (JARA), whose findings have now been published in the prestigious journal Nature Communications. The new finding radically revises the current theory and opens up possibilities for further applications. The research group has already filed a patent application for their first idea on how to improve data readout with the aid of battery voltage.

The Apr. 23, 2013 JARA news release, which originated the news item, provides some background information about data memory before going on to discuss the ReRAMs,

Conventional data memory works on the basis of electrons that are moved around and stored. However, even by atomic standards, electrons are extremely small. It is very difficult to control them, for example by means of relatively thick insulator walls, so that information will not be lost over time. This does not only limit storage density, it also costs a great deal of energy. For this reason, researchers are working feverishly all over the world on nanoelectronic components that make use of ions, i.e. charged atoms, for storing data. Ions are some thousands of times heavier that electrons and are therefore much easier to ‘hold down’. In this way, the individual storage elements can almost be reduced to atomic dimensions, which enormously improves the storage density.

Here’s how the ions behave in ReRAMs (from the news release),

In resistive switching memory cells (ReRAMs), ions behave on the nanometre scale in a similar manner to a battery. The cells have two electrodes, for example made of silver and platinum, at which the ions dissolve and then precipitate again. This changes the electrical resistance, which can be exploited for data storage. Furthermore, the reduction and oxidation processes also have another effect. They generate electric voltage. ReRAM cells are therefore not purely passive systems – they are also active electrochemical components. Consequently, they can be regarded as tiny batteries whose properties provide the key to the correct modelling and development of future data storage.

In complex experiments, the scientists from Forschungszentrum Jülich and RWTH Aachen University determined the battery voltage of typical representatives of ReRAM cells and compared them with theoretical values. This comparison revealed other properties (such as ionic resistance) that were previously neither known nor accessible. “Looking back, the presence of a battery voltage in ReRAMs is self-evident. But during the nine-month review process of the paper now published we had to do a lot of persuading, since the battery voltage in ReRAM cells can have three different basic causes, and the assignment of the correct cause is anything but trivial,” says Dr. Ilia Valov, the electrochemist in Prof. Rainer Waser’s research group.

This discovery could lead to optimizing ReRAMs and exploiting them in new applications (from the news release),

“The new findings will help to solve a central puzzle of international ReRAM research,” says Prof. Rainer Waser, deputy spokesman of the collaborative research centre SFB 917 ‘Nanoswitches’ established in 2011. In recent years, these puzzling aspects include unexplained long-term drift phenomena or systematic parameter deviations, which had been attributed to fabrication methods. “In the light of this new knowledge, it is possible to specifically optimize the design of the ReRAM cells, and it may be possible to discover new ways of exploiting the cells’ battery voltage for completely new applications, which were previously beyond the reach of technical possibilities,” adds Waser, whose group has been collaborating for years with companies such as Intel and Samsung Electronics in the field of ReRAM elements.

The part I found most interesting, given my interest in memristors, is this bit about extending the memristor theory, from the news release,

The new finding is of central significance, in particular, for the theoretical description of the memory components. To date, ReRAM cells have been described with the aid of the concept of memristors – a portmanteau word composed of “memory” and “resistor”. The theoretical concept of memristors can be traced back to Leon Chua in the 1970s. It was first applied to ReRAM cells by the IT company Hewlett-Packard in 2008. It aims at the permanent storage of information by changing the electrical resistance. The memristor theory leads to an important restriction. It is limited to passive components. “The demonstrated internal battery voltage of ReRAM elements clearly violates the mathematical construct of the memristor theory. This theory must be expanded to a whole new theory – to properly describe the ReRAM elements,” says Dr. Eike Linn, the specialist for circuit concepts in the group of authors. [emphases mine] This also places the development of all micro- and nanoelectronic chips on a completely new footing.

Here’s a link to and a citation for the paper,

Nanobatteries in redox-based resistive switches require extension of memristor theory by I. Valov,  E. Linn, S. Tappertzhofen,  S. Schmelzer,  J. van den Hurk,  F. Lentz,  & R. Waser. Nature Communications 4, Article number: 1771 doi:10.1038/ncomms2784 Published 23 April 2013

This paper is open access (as of this writing).

Here’s a list of my 2013 postings on memristors and memristive devices,

2.5M Euros for Ireland’s John Boland and his memristive nanowires (Apr. 4, 2013 posting)

How to use a memristor to create an artificial brain (Feb. 26, 2013 posting)

CeNSE (Central Nervous System of the Earth) and billions of tiny sensors from HP plus a memristor update (Feb. 7, 2013 posting)

For anyone who cares to search the blog, there are several more.

Samsung ‘GROs’ graphene-based micro-antennas and a brief bit about the business of nanotechnology

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A Feb. 22, 2013 news item on Nanowerk highlights a Samsung university grant (GRO) programme which announced funding for graphene-based micro-antennas,

The Graphene-Enabled Wireless Communication project, one of the award-winning proposals under the Samsung Global Research Outreach (GRO) programme, aims to use graphene antennas to implement wireless communication over very short distances (no more than a centimetre) with high-capacity information transmission (tens or hundreds of gigabits per second). Antennas made ??of [sic] graphene could radiate electromagnetic waves in the terahertz band and would allow for high-speed information transmission. Thanks to the unique properties of this nanomaterial, the new graphene-based antenna technology would also make it possible to manufacture antennas a thousand times smaller than those currently used.

The GRO programme—an annual call for research proposals by the Samsung Advanced Institute of Technology (Seoul, South Korea)—has provided the UPC-led project with US$120,000 in financial support.

The Graphene-Enabled Wireless Communication project is a joint project (from the news item; Note: A link has been removed),

“Graphene-Enabled Wireless Communications” – a proposal submitted by an interdepartmental team based at the Universitat Politècnica de Catalunya, BarcelonaTech (UPC) and the Georgia Institute of Technology (Georgia Tech)—will receive US$120,000 to develop micrometre-scale graphene antennas capable of transmitting information at a high speed over very short distances. The project will be carried out in the coming months.

…

The Graphene-Enabled Wireless Communication project, one of the award-winning proposals under the Samsung Global Research Outreach (GRO) programme, aims to use graphene antennas to implement wireless communication over very short distances (no more than a centimetre) with high-capacity information transmission (tens or hundreds of gigabits per second). Antennas made ??of graphene could radiate electromagnetic waves in the terahertz band and would allow for high-speed information transmission. Thanks to the unique properties of this nanomaterial, the new graphene-based antenna technology would also make it possible to manufacture antennas a thousand times smaller than those currently used.

There’s more about the Graphene-Enabled Wireless Communication project here,

 A remarkably promising application of graphene is that of Graphene-enabled Wireless Communications (GWC). GWC advocate for the use of graphene-based plasmonic antennas –graphennas, see Fig. 1- whose plasmonic effects allow them to radiate EM waves in the terahertz band (0.1 – 10 THz). Moreover, preliminary results sustain that this frequency band is up to two orders of magnitude below the optical frequencies at which metallic antennas of the same size resonate, thereby enhancing the transmission range of graphene-based antennas and lowering the requirements on the corresponding transceivers. In short, graphene enables the implementation of nano-antennas just a few micrometers in size that are not doable with traditional metallic materials.

Thanks to both the reduced size and unique radiation capabilities of ZZ, GWC may represent a breakthrough in the ultra-short range communications research area. In this project we will study the application of GWC within the scenario of off-chip communication, which includes communication between different chips of a given device, e.g. a cell phone.

A new term, graphenna, appears to be have been coined. The news item goes on to offer more detail about the project and about the number of collaborating institutions,

The first stage of the project, launched in October 2012, focuses on the theoretical foundations of wireless communications over short distances using graphene antennas. In particular, the group is analysing the behaviour of electromagnetic waves in the terahertz band for very short distances, and investigating how coding and modulation schemes can be adapted to achieve high transmission rates while maintaining low power consumption.

…

The group believes the main benefits of the project in the medium term will derive from its application for internal communication in multicore processors. Processors of this type have a number of sub-processors that share and execute tasks in parallel. The application of wireless communication in this area will make it possible to integrate thousands of sub-processors within a single processor, which is not feasible with current communication systems.

The results of the project will lead to an increase in the computational performance of these devices. This improvement would allow large amounts of data to be processed at very high speed, which would be very useful for streamlining data management at processing centres (“big data”) used, for example, in systems like Facebook and Google. The project, which builds on previous results obtained with the collaboration of the University of Wuppertal in Germany, the Royal Institute of Technology (KTH) in Sweden, and Georgia Tech in the United States, is expected to yield its first results in April 2013.

The project is being carried out by the NaNoNetworking Centre in Catalonia (N3Cat), a network formed at the initiative of researchers with the UPC’s departments of Electronic Engineering and Computer Architecture, together with colleagues at Georgia Tech.

Anyone interested in  Samsung’s GRO programme can find more here,

The SAMSUNG Global Research Outreach (GRO) program, open to leading universities around the world, is Samsung Electronics, Co., Ltd. & related Samsung companies (SAMSUNG)’s annual call for research proposals.

As this Samsung-funded research project is being announced, Dexter Johnson details the business failure of NanoInk in a Feb. 22, 2013 posting on his Nanoclast blog (on the IEEE [International Institute of Electrical and Electronics Engineers] website), Note: Links have been removed,

One of the United State’s first nanotechnology companies, NanoInk, has gone belly up, joining a host of high-profile nanotechnology-based companies that have shuttered their doors in the last 12 months: Konarka, A123 Systems and Ener1.

These other three companies were all tied to the energy markets (solar in the case of Konarka and batteries for both A123 and Ener1), which are typically volatile, with a fair number of shuttered businesses dotting their landscapes. But NanoInk is a venerable old company in comparison to these other three and is more in what could be characterized as the “picks-and-shovels” side of the nanotechnology business, microscopy tools.

Dexter goes on to provide an  analysis of the NanoInk situation which makes for some very interesting reading along with the comments—some feisty, some not—his posting has provoked.

I am juxtaposing the Samsung funding announcement with this mention of Dexter’s piece regarding a  ‘nanotechnology’ business failure in an effort to provide some balance between enthusiasm for the research and the realities of developing businesses and products based on that research.